2009 |
50 | EE | Inna Vaisband,
Ran Ginosar,
Avinoam Kolodny,
Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction.
ACM Great Lakes Symposium on VLSI 2009: 285-290 |
2008 |
49 | EE | Rostislav (Reuven) Dobkin,
Ran Ginosar:
Fast Universal Synchronizers.
PATMOS 2008: 199-208 |
48 | EE | Arkadiy Morgenshtein,
Eby G. Friedman,
Ran Ginosar,
Avinoam Kolodny:
Timing optimization in logic with interconnect.
SLIP 2008: 19-26 |
47 | EE | Rostislav (Reuven) Dobkin,
Arkadiy Morgenshtein,
Avinoam Kolodny,
Ran Ginosar:
Parallel vs. serial on-chip communication.
SLIP 2008: 43-50 |
46 | EE | A. Elyada,
Ran Ginosar,
U. Weiser:
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors.
IEEE Trans. VLSI Syst. 16(9): 1243-1248 (2008) |
2007 |
45 | EE | Rostislav (Reuven) Dobkin,
Yevgeny Perelman,
Tuvia Liran,
Ran Ginosar,
Avinoam Kolodny:
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.
ASYNC 2007: 3-14 |
44 | EE | Evgeny Bolotin,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Routing table minimization for irregular mesh NoCs.
DATE 2007: 942-947 |
43 | EE | Evgeny Bolotin,
Zvika Guz,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
The Power of Priority: NoC Based Distributed Cache Coherency.
NOCS 2007: 117-126 |
42 | EE | Isask'har Walter,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Access Regulation to Hot-Modules in Wormhole NoCs.
NOCS 2007: 137-148 |
41 | EE | Rostislav (Reuven) Dobkin,
Ran Ginosar,
Israel Cidon:
QNoC Asynchronous Router with Dynamic Virtual Channel Allocation.
NOCS 2007: 218 |
40 | EE | Rami Rom,
Jacob Erel,
Michael Glikson,
Randy A. Lieberman,
Kobi Rosenblum,
Ofer Binah,
Ran Ginosar,
David L. Hayes:
Adaptive Cardiac Resynchronization Therapy Device Based on Spiking Neurons Architecture and Reinforcement Learning Scheme.
IEEE Transactions on Neural Networks 18(2): 542-550 (2007) |
2006 |
39 | EE | Rostislav (Reuven) Dobkin,
Ran Ginosar,
Avinoam Kolodny:
Fast Asynchronous Shift Register for Bit-Serial Communication.
ASYNC 2006: 117-127 |
38 | EE | Zvika Guz,
Isask'har Walter,
Evgeny Bolotin,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Efficient link capacity and QoS design for network-on-chip.
DATE 2006: 9-14 |
37 | EE | Uri Frank,
Tsachy Kapschitz,
Ran Ginosar:
A predictive synchronizer for periodic clock domains.
Formal Methods in System Design 28(2): 171-186 (2006) |
36 | EE | Rostislav (Reuven) Dobkin,
Ran Ginosar,
Christos P. Sotiriou:
High Rate Data Synchronization in GALS SoCs.
IEEE Trans. VLSI Syst. 14(10): 1063-1074 (2006) |
35 | EE | Ilya Obridko,
Ran Ginosar:
Minimal Energy Asynchronous Dynamic Adders.
IEEE Trans. VLSI Syst. 14(9): 1043-1047 (2006) |
2005 |
34 | EE | Rostislav (Reuven) Dobkin,
Victoria Vishnyakov,
Eyal Friedman,
Ran Ginosar:
An Asynchronous Router for Multiple Service Levels Networks on Chip.
ASYNC 2005: 44-53 |
33 | EE | Tsachy Kapschitz,
Ran Ginosar:
Formal Verification of Synchronizers.
CHARME 2005: 359-362 |
32 | EE | Arkadiy Morgenshtein,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Low-leakage repeaters for NoC interconnects.
ISCAS (1) 2005: 600-603 |
31 | EE | Ilya Obridko,
Ran Ginosar:
Low energy asynchronous architectures.
ISCAS (5) 2005: 5238-5241 |
30 | EE | Rostislav (Reuven) Dobkin,
Michael Peleg,
Ran Ginosar:
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
IEEE Trans. VLSI Syst. 13(4): 427-438 (2005) |
2004 |
29 | EE | Rostislav (Reuven) Dobkin,
Ran Ginosar,
Christos P. Sotiriou:
Data Synchronization Issues in GALS SoCs.
ASYNC 2004: 170-180 |
28 | EE | Alex Branover,
Rakefet Kol,
Ran Ginosar:
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones.
DATE 2004: 870-877 |
27 | EE | Uri Frank,
Ran Ginosar:
A Predictive Synchronizer for Periodic Clock Domains.
PATMOS 2004: 402-412 |
26 | EE | Arkadiy Morgenshtein,
Michael Moreinis,
Ran Ginosar:
Asynchronous gate-diffusion-input (GDI) circuits.
IEEE Trans. VLSI Syst. 12(8): 847-856 (2004) |
25 | EE | Evgeny Bolotin,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
Cost considerations in network on chip.
Integration 38(1): 19-42 (2004) |
24 | EE | Evgeny Bolotin,
Israel Cidon,
Ran Ginosar,
Avinoam Kolodny:
QNoC: QoS architecture and design process for network on chip.
Journal of Systems Architecture 50(2-3): 105-128 (2004) |
2003 |
23 | EE | Yaron Semiat,
Ran Ginosar:
Timing Measurements of Synchronization Circuits.
ASYNC 2003: 68-77 |
22 | EE | Ran Ginosar:
Fourteen Ways to Fool Your Synchronizer.
ASYNC 2003: 89-97 |
21 | EE | Ken S. Stevens,
Ran Ginosar,
Shai Rotem:
Relative timing [asynchronous design].
IEEE Trans. VLSI Syst. 11(1): 129-140 (2003) |
20 | EE | Y. Elboim,
Avinoam Kolodny,
Ran Ginosar:
A clock-tuning circuit for system-on-chip.
IEEE Trans. VLSI Syst. 11(4): 616-626 (2003) |
1999 |
19 | EE | Ken S. Stevens,
Shai Rotem,
Ran Ginosar:
Relative Timing.
ASYNC 1999: 208-218 |
18 | EE | Shai Rotem,
Ken S. Stevens,
Charles Dike,
Marly Roncken,
Boris Agapiev,
Ran Ginosar,
Rakefet Kol,
Peter A. Beerel,
Chris J. Myers,
Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder.
ASYNC 1999: 60-70 |
17 | EE | Ken S. Stevens,
Shai Rotem,
Steven M. Burns,
Jordi Cortadella,
Ran Ginosar,
Michael Kishinevsky,
Marly Roncken:
CAD Directions for High Performance Asynchronous Circuits.
DAC 1999: 116-121 |
1998 |
16 | EE | Wei-Chun Chou,
Peter A. Beerel,
Ran Ginosar,
Rakefet Kol,
Chris J. Myers,
Shai Rotem,
Ken S. Stevens,
Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
ASYNC 1998: 80- |
15 | EE | Uzi Zangi,
Ran Ginosar:
A low power video processor.
ISLPED 1998: 136-138 |
14 | EE | Rakefet Kol,
Ran Ginosar:
Kin: A High Performance Asynchronous Processor Architecture.
International Conference on Supercomputing 1998: 433-440 |
1997 |
13 | | Rakefet Kol,
Ran Ginosar:
A Double-Latched Asynchronous Pipeline.
ICCD 1997: 706-712 |
1995 |
12 | EE | Ilana David,
Ran Ginosar,
Michael Yoeli:
Self-timed is self-checking.
J. Electronic Testing 6(2): 219-228 (1995) |
1993 |
11 | | Ilana David,
Ran Ginosar,
Michael Yoeli:
Self-Timed Architecture of a Reduced Instruction Set Computer.
Asynchronous Design Methodologies 1993: 29-43 |
10 | EE | Alan Rotman,
Ran Ginosar:
Control unit synthesis from a high-level language.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 162-167 (1993) |
1992 |
9 | | Ilana David,
Ran Ginosar,
Michael Yoeli:
Implementing Sequential Machines as Self-Timed Circuits.
IEEE Trans. Computers 41(1): 12-17 (1992) |
8 | | Ilana David,
Ran Ginosar,
Michael Yoeli:
An Efficient Implementation of Boolean Functions as Self-Timed Circuits.
IEEE Trans. Computers 41(1): 2-11 (1992) |
1991 |
7 | | Arie Harsat,
Ran Ginosar:
CARMEL-4: The Unify-Spawn Machine for FCP.
ICLP 1991: 840-854 |
1990 |
6 | | Arie Harsat,
Ran Ginosar:
An Extended RISC Methodology and its Application to FCP.
ICLP 1990: 67-82 |
1988 |
5 | | Arie Harsat,
Ran Ginosar:
CARMEL-2: A Second Generation VLSI Architecture for Flat Concurrent Prolog.
FGCS 1988: 962-969 |
1985 |
4 | | Ran Ginosar,
Dwight D. Hill:
Design and Implementation of Switching Systems for Parallel Processors.
ICPP 1985: 674-680 |
1982 |
3 | | Bruce W. Arden,
Ran Ginosar:
MP/C: A Multiprocessor/Computer Architecture.
IEEE Trans. Computers 31(5): 455-473 (1982) |
1981 |
2 | | Bruce W. Arden,
Ran Ginosar:
A Single-Relation Module for a Data Base Machine.
ISCA 1981: 227-238 |
1 | | Bruce W. Arden,
Ran Ginosar:
MP/C: A Multiprocessor/Computer Architecture.
ISCA 1981: 3-20 |