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Toru Iwata

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2008
4EETakefumi Yoshikawa, T. Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi: An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. IEEE Trans. VLSI Syst. 16(9): 1187-1198 (2008)
2005
3EETakefumi Yoshikawa, Tsuyoshi Ebuchi, Yukio Arima, Toru Iwata: A Spread Spectrum Clock Generator Using Digital Tracking Scheme. IEICE Transactions 88-C(6): 1288-1289 (2005)
1997
2EEHiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa: A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. VLSI Syst. 5(4): 377-387 (1997)
1996
1EEHiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa: A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED 1996: 49-54

Coauthor Index

1Hironori Akamatsu [1] [2]
2Yukio Arima [3] [4]
3Tsuyoshi Ebuchi [3] [4]
4T. Hirata [4]
5Akira Matsuzawa [1] [2]
6Hiroyuki Yamauchi [1] [2] [4]
7Takefumi Yoshikawa [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)