| 2008 |
|---|
| 6 | EE | Tung-Han Tsai,
Chin-Lin Chen,
Ching-Li Lee,
Chua-Chin Wang:
Power-saving nano-scale DRAMs with an adaptive refreshing clock generator.
ISCAS 2008: 612-615 |
| 5 | EE | Chua-Chin Wang,
Chi-Chun Huang,
Ching-Li Lee,
Tsai-Wen Cheng:
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic.
IEEE Trans. VLSI Syst. 16(5): 594-598 (2008) |
| 4 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Chi-Chun Huang,
Ching-Li Lee,
Tian-Hau Chen,
Wun-Ji Lin,
Ron Hu:
A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors.
Journal of Circuits, Systems, and Computers 17(5): 943-956 (2008) |
| 2006 |
|---|
| 3 | EE | Chua-Chin Wang,
Gang-Neng Sung,
Ming-Kai Chang,
Ching-Li Lee,
Cheng-Mu Wu,
Ju-Ya Chen:
A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers.
APCCAS 2006: 1112-1115 |
| 2 | EE | Chua-Chin Wang,
Ching-Li Lee,
Wun-Ji Lin:
A 4-Kb low power 4-T SRAM design with negative word-line gate drive.
ISCAS 2006 |
| 2005 |
|---|
| 1 | EE | Chua-Chin Wang,
Ching-Li Lee,
Li-Ping Lin,
Yih-Long Tseng:
Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC.
ISCAS (1) 2005: 356-359 |
