| |
| 2008 | ||
|---|---|---|
| 3 | EE | Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van: Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor. IEEE Trans. VLSI Syst. 16(8): 1058-1071 (2008) |
| 2007 | ||
| 2 | EE | Lan-Da Van, Chin-Teng Lin, Yuan-Chu Yu: VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design. IEICE Transactions 90-A(8): 1644-1652 (2007) |
| 2006 | ||
| 1 | EE | Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van: A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application. ISCAS 2006 |
| 1 | Chin-Teng Lin | [1] [2] [3] |
| 2 | Lan-Da Van | [1] [2] [3] |