An-Yeu Wu

2008
35	EE	Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu: Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. ISCAS 2008: 3150-3153
34	EE	Huifei Rao, Jie Chen, V. H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu: An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. ISCAS 2008: 608-611
33	EE	Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Low-power traceback MAP decoding for double-binary convolutional turbo decoder. ISCAS 2008: 736-739
32	EE	Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Keng-Hsien Huang, An-Yeu Wu: Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks. IEEE Trans. Computers 57(9): 1156-1168 (2008)
31	EE	Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. IEEE Trans. VLSI Syst. 16(10): 1358-1371 (2008)
30	EE	I-Chyn Wey, You-Gang Chen, An-Yeu Wu: Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. VLSI Syst. 16(12): 1708-1712 (2008)
29	EE	Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu: Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme. Signal Processing Systems 52(1): 59-73 (2008)
2007
28	EE	Chih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien: A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. ISCAS 2007: 1113-1116
27	EE	Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao: Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. ISCAS 2007: 1803-1806
26	EE	Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu: Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS 2007: 869-872
25	EE	Wein-Tsung Shen, Chih-Hao Chao, Yu-Kuang Lien, An-Yeu Wu: A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network. NOCS 2007: 317-322
24	EE	Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee: Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. VLSI Syst. 15(2): 236-240 (2007)
23	EE	Fan-Min Li, An-Yeu Wu: On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold. IEEE Transactions on Signal Processing 55(11): 5506-5516 (2007)
2006
22	EE	Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. ISCAS 2006
21	EE	Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu: A portable all-digital pulsewidth control loop for SOC applications. ISCAS 2006
20	EE	Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai Tsao: DSP engine design for LINC wireless transmitter systems. ISCAS 2006
2005
19	EE	Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu: A memory-reduced log-MAP kernel for turbo decoder. ISCAS (2) 2005: 1032-1035
18	EE	I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu: A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) 2005: 1074-1077
17	EE	Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu: A scalable DCO design for portable ADPLL designs. ISCAS (6) 2005: 5449-5452
16	EE	Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu: Digital signal processing engine design for polar transmitter in wireless communication systems. ISCAS (6) 2005: 6026-6029
15	EE	Chih-Hsiu Lin, An-Yeu Wu: Soft-threshold-based multilayer decision feedback equalizer (STM-DFE) algorithm and VLSI architecture. IEEE Transactions on Signal Processing 53(8-2): 3325-3336 (2005)
2004
14		Ching-Hua Wen, Huai-Yi Hsu, Hung Yang Ko, An-Yeu Wu: Least squares approximation-based ROM-free direct digital frequency synthesizer. ISCAS (2) 2004: 701-704
13		Kai Huang, Fan-Min Li, Pei-Ling Shen, An-Yeu Wu: VLSI design of dual-mode Viterbi/turbo decoder for 3GPP. ISCAS (2) 2004: 773-776
12		Hsiu-Ping Lin, Nancy Fang-Yih Chen, Jyh-Ting Lai, An-Yeu Wu: 1000BASE-T Gigabit Ethernet baseband DSP IC design. ISCAS (4) 2004: 401-404
11		Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu: A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. ISCAS (5) 2004: 293-296
10		Meng-Da Yang, An-Yeu Wu, Jyh-Ting Lai: High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. IEEE Trans. VLSI Syst. 12(2): 218-226 (2004)
2003
9	EE	Jen-Chih Kuo, Ching-Hua Wen, An-Yeu Wu: Implementation of a programmable 64/spl sim/2048-point FFT/IFFT processor for OFDM-based communication systems. ISCAS (2) 2003: 121-124
8	EE	Huai-Yi Hsu, Sheng-Feng Wang, An-Yeu Wu: A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm. VLSI Signal Processing 34(3): 251-259 (2003)
2002
7	EE	Meng-Da Yang, An-Yeu Wu: A new pipelined adaptive DFE architecture with improved convergence rate. ISCAS (4) 2002: 213-216
6	EE	Cheng-Shing Wu, An-Yeu Wu: A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller. ISCAS (5) 2002: 453-456
2001
5	EE	Chi-Li Yu, An-Yeu Wu: An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. ISCAS (4) 2001: 250-253
1998
4	EE	An-Yeu Wu, K. J. Ray Liu: Algorithm-based low-power transform coding architectures: the multirate approach. IEEE Trans. VLSI Syst. 6(4): 707-718 (1998)
1995
3	EE	An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-Chieh Liu: Parallel programmable video co-processor design. ICIP 1995: 61-64
1994
2		An-Yeu Wu, K. J. Ray Liu: A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. ISCAS 1994: 155-158
1993
1		K. J. Ray Liu, An-Yeu Wu: A Multi-layer 2-D Adaptive Filtering Architecture Based on McClellan Transformation. ISCAS 1993: 1999-2002

Coauthor Index

1	Woon Tiong Ang	[27] [34]
2	Lung-Hao Chang	[18]
3	Shih-Hung Chang	[18]
4	Chih-Hao Chao	[25] [28] [32]
5	Chun-Yu Chen	[33]
6	Jie Chen	[27] [34]
7	Nancy Fang-Yih Chen	[12]
8	Yen-Liang Chen	[29] [35]
9	You-Gang Chen	[18] [26] [30]
10	Weber Chien	[28]
11	Huai-Yi Hsu	[8] [14]
12	Ming-Feng Hsu	[29]
13	Chun-Hsiang Huang	[32]
14	Kai Huang	[13]
15	Keng-Hsien Huang	[32]
16	Kai-Yuan Jheng	[11] [20]
17	Shyh-Jye Jou	[11]
18	Hung Yang Ko	[14] [16]
19	Jen-Chih Kuo	[9]
20	Yen-Lin Kuo	[28]
21	Jyh-Ting Lai	[10] [12] [24] [29]
22	Chien-Hsiung Lee	[24]
23	Fan-Min Li	[13] [23] [31]
24	Yu-Kuang Lien	[25]
25	Cheng-Hung Lin	[19] [31] [33]
26	Chih-Hsiu Lin	[15]
27	Hsiu-Ping Lin	[12]
28	Shu-Yen Lin	[32]
29	K. J. Ray Liu	[1] [2] [3] [4]
30	Shang-Chieh Liu	[3]
31	Arun Raghupathy	[3]
32	Huifei Rao	[27] [34]
33	Pei-Ling Shen	[13]
34	Wein-Tsung Shen	[25]
35	Tsung-Han Tsai	[19]
36	Hen-Wai Tsao	[20]
37	Sheng-Feng Wang	[8]
38	Wei Wang	[17] [21] [22]
39	Yi-Chiuan Wang	[16] [20]
40	Ching-Hua Wen	[9] [14]
41	I-Chyn Wey	[17] [18] [21] [22] [26] [27] [30] [34]
42	Cheng-Shing Wu	[6]
43	Chia-Tsun Wu	[17] [21] [22]
44	Meng-Da Yang	[7] [10]
45	Jhao-Ji Ye	[26]
46	Changhong Yu	[27]
47	Chi-Li Yu	[5]
48	Cheng-Zhou Zhan	[35]
49	Hong Zhao	[27]
50	V. H. Zhao	[34]

Colors in the list of coauthors