| 2008 |
|---|
| 7 | EE | Mitchell J. Myjak,
José G. Delgado-Frias:
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance.
IEEE Trans. VLSI Syst. 16(1): 14-23 (2008) |
| 2006 |
|---|
| 6 | EE | Mitchell J. Myjak,
José G. Delgado-Frias:
Superpipelined reconfigurable hardware for DSP.
ISCAS 2006 |
| 2005 |
|---|
| 5 | | Mitchell J. Myjak,
José G. Delgado-Frias:
A Symmetric Differential Clock Generator for Bit-Serial Hardware.
CDES 2005: 159-164 |
| 4 | | Daniel R. Blum,
Mitchell J. Myjak,
José G. Delgado-Frias:
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.
CDES 2005: 28-34 |
| 2004 |
|---|
| 3 | | Mitchell J. Myjak,
Fredrick L. Anderson,
José G. Delgado-Frias:
H-Tree Interconnection Structure for Reconfigurable DSP Hardware.
ERSA 2004: 170-176 |
| 2 | EE | Mitchell J. Myjak,
José G. Delgado-Frias:
Pipelined Multipliers for Reconfigurable Hardware.
IPDPS 2004 |
| 2003 |
|---|
| 1 | | Mitchell J. Myjak,
José G. Delgado-Frias:
A Two-Level Reconfigurable Architecture for Digital Signal Processing.
VLSI 2003: 21-27 |
