2008 |
10 | EE | Tung-Chieh Chen,
Ashutosh Chakraborty,
David Z. Pan:
An integrated nonlinear placement framework with congestion and porosity aware buffer planning.
DAC 2008: 702-707 |
9 | EE | Ashutosh Chakraborty,
Sean X. Shi,
David Z. Pan:
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.
DATE 2008: 849-855 |
8 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst. 16(6): 639-649 (2008) |
7 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration 41(1): 2-8 (2008) |
2006 |
6 | EE | Ashutosh Chakraborty,
Prassanna Sithambaram,
Karthik Duraisami,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Thermal resilient bounded-skew clock tree optimization methodology.
DATE 2006: 832-837 |
5 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS 2006 |
4 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED 2006: 162-167 |
3 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS 2006: 214-224 |
2005 |
2 | EE | Ashutosh Chakraborty,
Enrico Macii,
Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.
PATMOS 2005: 297-307 |
2003 |
1 | EE | Pradeep Varma,
Ashutosh Chakraborty:
Low-Voltage, Double-Edge-Triggered Flip Flop.
PATMOS 2003: 11-20 |