2009 | ||
---|---|---|
54 | EE | Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design 2009: 281-286 |
53 | EE | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
52 | EE | Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A SIMD optimization framework for retargetable compilers. TACO 6(1): (2009) |
2008 | ||
51 | EE | Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Multiprocessor performance estimation using hybrid simulation. DAC 2008: 325-330 |
50 | EE | Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda: MAPS: an integrated framework for MPSoC application parallelization. DAC 2008: 754-759 |
49 | EE | Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE 2008: 1334-1339 |
48 | EE | Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh: Retargetable Code Optimization for Predicated Execution. DATE 2008: 1492-1497 |
47 | EE | Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle: System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. DATE 2008 |
46 | EE | I-Wei Lai, Susanne Godtmann, Tzi-Dar Chiueh, Gerd Ascheid, Heinrich Meyr: Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI. ICC 2008: 1238-1242 |
45 | EE | Niels Hadaschik, Gerd Ascheid: Deriving a Joint Interference Detection and Channel Estimation for WB-OFDM from EM-MAP Theory. ICC 2008: 1322-1327 |
44 | EE | Susanne Godtmann, Niels Hadaschik, Wolfgang Steinert, Gerd Ascheid: A Concept for Data-Aided Carrier Frequency Estimation at Low Signal-To-Noise Ratios. ICC 2008: 463-467 |
43 | EE | Susanne Godtmann, Helge Luders, Gerd Ascheid, Peter Vary: A Bit-Mapping Strategy for Joint Iterative Channel Estimation and Turbo-Decoding. VTC Fall 2008: 1-5 |
42 | EE | Markus Jordan, Martin Senst, Gerd Ascheid, Heinrich Meyr: Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation. VTC Spring 2008: 275-279 |
41 | EE | Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embedded Comput. Syst. 7(4): (2008) |
40 | EE | Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid: A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008) |
39 | EE | Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Power-efficient Instruction Encoding Optimization for Various Architecture Classes. JCP 3(3): 25-38 (2008) |
2007 | ||
38 | EE | Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: A fast and generic hybrid simulation approach using C virtual machine. CASES 2007: 3-12 |
37 | EE | Hanno Scharwächter, Jonghee M. Yoon, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr: A code-generator generator for multi-output instructions. CODES+ISSS 2007: 131-136 |
36 | EE | Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: HySim: a fast simulation framework for embedded software development. CODES+ISSS 2007: 75-80 |
35 | EE | Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE 2007: 1349-1354 |
34 | EE | Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Design space exploration of partially re-configurable embedded processors. DATE 2007: 319-324 |
33 | EE | Martin Senst, Markus Jordan, Meik Dorpinghaus, Michael Farber, Gerd Ascheid, Heinrich Meyr: Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems. GLOBECOM 2007: 3812-3816 |
32 | EE | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD 2007: 166-171 |
31 | EE | Anupam Chattopadhyay, Z. Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping 2007: 189-194 |
30 | EE | Markus Jordan, Gerd Ascheid, Heinrich Meyr: Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA. VTC Spring 2007: 1652-1656 |
29 | EE | Susanne Godtmann, André Pollok, Niels Hadaschik, Gerd Ascheid, Heinrich Meyr: On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization. VTC Spring 2007: 1723-1726 |
28 | EE | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
2006 | ||
27 | EE | Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren: Retargetable code optimization with SIMD instructions. CODES+ISSS 2006: 148-153 |
26 | EE | Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE 2006: 468-473 |
25 | EE | Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605 |
24 | EE | Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE 2006: 919-924 |
23 | EE | Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum 2006: 221-226 |
22 | EE | Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238 |
21 | EE | Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Memory Access Micro-Profiling for ASIP Design. DELTA 2006: 255-262 |
20 | EE | Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118 |
19 | EE | Harold Ishebabi, Gerd Ascheid, Heinrich Meyr, O. Atak, A. Atalar, E. Arikan: An efficient parallelization technique for high throughput FFT-ASIPs. ISCAS 2006 |
18 | EE | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. VLSI Signal Processing 43(2-3): 235-246 (2006) |
2005 | ||
17 | EE | Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers: Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP 2005: 154-160 |
16 | EE | Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel: A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 |
15 | EE | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel: Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS 2005: 249-254 |
14 | EE | Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Fine-grained application source code profiling for ASIP design. DAC 2005: 329-334 |
13 | EE | Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: C Compiler Retargeting Based on Instruction Semantics Models. DATE 2005: 1150-1155 |
12 | EE | Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE 2005: 876-881 |
11 | EE | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr: Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171 |
10 | Rainer Leupers, Gerd Ascheid: Digital Signal Processors. Handbook of Networked and Embedded Control Systems 2005: 279-294 | |
2004 | ||
9 | EE | Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE 2004: 1256-1263 |
8 | EE | Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE 2004: 1276-1283 |
7 | EE | Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl: RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160 |
6 | EE | Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS 2004: 138-148 |
5 | EE | Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: Early ISS Integration into Network-on-Chip Designs. SAMOS 2004: 443-452 |
4 | EE | Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS 2004: 463-473 |
3 | EE | Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr: ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES 2004: 33-46 |
2003 | ||
2 | EE | Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens: A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12 |
1 | EE | Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie: Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES 2003: 167-181 |