2009 |
16 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
2008 |
15 | EE | Anupam Chattopadhyay,
Xiaolin Chen,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
DATE 2008: 1334-1339 |
14 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 7(4): (2008) |
13 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Xiaolin Chen,
David Kammler,
Ling Hao,
Rainer Leupers,
Heinrich Meyr,
Gerd Ascheid:
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008) |
12 | EE | Diandian Zhang,
Anupam Chattopadhyay,
David Kammler,
Ernst Martin Witte,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
JCP 3(3): 25-38 (2008) |
2007 |
11 | EE | Anupam Chattopadhyay,
W. Ahmed,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors.
DATE 2007: 319-324 |
10 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering.
ICCAD 2007: 166-171 |
9 | EE | Anupam Chattopadhyay,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
IEEE International Workshop on Rapid System Prototyping 2007: 189-194 |
8 | EE | Anupam Chattopadhyay,
Diandian Zhang,
David Kammler,
Ernst Martin Witte:
Power-efficient Instruction Encoding Optimization for Embedded Processors.
VLSI Design 2007: 595-600 |
2006 |
7 | EE | Anupam Chattopadhyay,
B. Geukes,
David Kammler,
Ernst Martin Witte,
Oliver Schliebusch,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors.
DATE 2006: 600-605 |
6 | EE | Anupam Chattopadhyay,
Arnab Sinha,
Diandian Zhang,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design.
IEEE International Workshop on Rapid System Prototyping 2006: 110-118 |
2005 |
5 | EE | Mohammad Mostafizur Rahman Mozumdar,
Kingshuk Karuri,
Anupam Chattopadhyay,
Stefan Kraemer,
Hanno Scharwächter,
Heinrich Meyr,
Gerd Ascheid,
Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
ASAP 2005: 154-160 |
4 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr,
Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
ASP-DAC 2005: 280-285 |
3 | EE | Ernst Martin Witte,
Anupam Chattopadhyay,
Oliver Schliebusch,
David Kammler:
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.
ICCD 2005: 193-199 |
2 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Ernst Martin Witte,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
IEEE International Workshop on Rapid System Prototyping 2005: 165-171 |
2004 |
1 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Mario Steinert,
Gunnar Braun,
Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE 2004: 156-160 |