| |
| 2008 | ||
|---|---|---|
| 3 | EE | I-Chyn Wey, You-Gang Chen, An-Yeu Wu: Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. IEEE Trans. VLSI Syst. 16(12): 1708-1712 (2008) |
| 2007 | ||
| 2 | EE | Jhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu: Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. ISCAS 2007: 869-872 |
| 2005 | ||
| 1 | EE | I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu: A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ISCAS (2) 2005: 1074-1077 |
| 1 | Lung-Hao Chang | [1] |
| 2 | Shih-Hung Chang | [1] |
| 3 | I-Chyn Wey | [1] [2] [3] |
| 4 | An-Yeu Wu | [1] [2] [3] |
| 5 | Jhao-Ji Ye | [2] |