Yuh-Fang Tsai

2008
13	EE	Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008)
2007
12	EE	Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network CoRR abs/0710.4731: (2007)
2006
11	EE	Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006)
2005
10	EE	Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231
9	EE	Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524
8	EE	Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379
2004
7	EE	Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58
6	EE	Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Characterization and modeling of run-time techniques for leakage power reduction. IEEE Trans. VLSI Syst. 12(11): 1221-1233 (2004)
2003
5	EE	Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Implications of technology scaling on leakage reduction techniques. DAC 2003: 187-190
4	EE	Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Managing Leakage Energy in Cache Hierarchies. J. Instruction-Level Parallelism 5: (2003)
2002
3	EE	Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Leakage Energy Management in Cache Hierarchies. IEEE PACT 2002: 131-140
2	EE	David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin: Evaluating Run-Time Techniques for Leakage Power Reduction. VLSI Design 2002: 31-38
2001
1	EE	Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113

Coauthor Index

1	D. E. Duarte	[6]
2	David Duarte	[1] [2] [5] [11]
3	Aman Gayasen	[7]
4	Mary Jane Irwin	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
5	Ismail Kadayif	[3] [4]
6	Mahmut T. Kandemir	[1] [3] [4] [7] [11]
7	Lin Li	[3] [4]
8	Anand Sivasubramaniam	[3] [4]
9	Tim Tuan	[7]
10	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
11	Feng Wang	[13]
12	Yuan Xie	[8] [9] [10] [12] [13]
13	Wei Zhang	[1] [11]