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Yuh-Fang Tsai

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2008
13EEYuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008)
2007
12EEYuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network CoRR abs/0710.4731: (2007)
2006
11EEWei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embedded Comput. Syst. 5(1): 1-28 (2006)
2005
10EEYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231
9EEYuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524
8EEYuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379
2004
7EEAman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan: Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58
6EEYuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Characterization and modeling of run-time techniques for leakage power reduction. IEEE Trans. VLSI Syst. 12(11): 1221-1233 (2004)
2003
5EEYuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin: Implications of technology scaling on leakage reduction techniques. DAC 2003: 187-190
4EELin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Managing Leakage Energy in Cache Hierarchies. J. Instruction-Level Parallelism 5: (2003)
2002
3EELin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam: Leakage Energy Management in Cache Hierarchies. IEEE PACT 2002: 131-140
2EEDavid Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin: Evaluating Run-Time Techniques for Leakage Power Reduction. VLSI Design 2002: 31-38
2001
1EEWei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai: Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113

Coauthor Index

1D. E. Duarte [6]
2David Duarte [1] [2] [5] [11]
3Aman Gayasen [7]
4Mary Jane Irwin [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
5Ismail Kadayif [3] [4]
6Mahmut T. Kandemir [1] [3] [4] [7] [11]
7Lin Li [3] [4]
8Anand Sivasubramaniam [3] [4]
9Tim Tuan [7]
10Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
11Feng Wang [13]
12Yuan Xie [8] [9] [10] [12] [13]
13Wei Zhang [1] [11]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)