| 2009 |
|---|
| 9 | EE | Cheng-Hung Lin,
Hsien-Sheng Hsiao:
Hierarchical state machine architecture for regular expression pattern matching.
ACM Great Lakes Symposium on VLSI 2009: 133-136 |
| 2008 |
|---|
| 8 | EE | Cheng-Hung Lin,
Chun-Yu Chen,
An-Yeu Wu:
Low-power traceback MAP decoding for double-binary convolutional turbo decoder.
ISCAS 2008: 736-739 |
| 7 | EE | Fan-Min Li,
Cheng-Hung Lin,
An-Yeu Wu:
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.
IEEE Trans. VLSI Syst. 16(10): 1358-1371 (2008) |
| 2007 |
|---|
| 6 | EE | Cheng-Hung Lin,
Yu-Tang Tai,
Shih-Chieh Chang:
Optimization of pattern matching algorithm for memory based architecture.
ANCS 2007: 11-16 |
| 5 | EE | Yu-Min Kuo,
Cheng-Hung Lin,
Chun-Yao Wang,
Shih-Chieh Chang,
Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
ISQED 2007: 344-349 |
| 4 | EE | Cheng-Hung Lin,
Chih-Tsun Huang,
Chang-Ping Jiang,
Shih-Chieh Chang:
Optimization of Pattern Matching Circuits for Regular Expression on FPGA.
IEEE Trans. VLSI Syst. 15(12): 1303-1310 (2007) |
| 2006 |
|---|
| 3 | EE | Cheng-Hung Lin,
Chih-Tsun Huang,
Chang-Ping Jiang,
Shih-Chieh Chang:
Optimization of regular expression pattern matching circuits on FPGA.
DATE Designers' Forum 2006: 12-17 |
| 2005 |
|---|
| 2 | EE | Cheng-Hung Lin,
Yung-Chang Huang,
Shih-Chieh Chang,
Wen-Ben Jone:
Design and design automation of rectification logic for engineering change.
ASP-DAC 2005: 1006-1009 |
| 1 | EE | Tsung-Han Tsai,
Cheng-Hung Lin,
An-Yeu Wu:
A memory-reduced log-MAP kernel for turbo decoder.
ISCAS (2) 2005: 1032-1035 |
