2008 |
14 | EE | Nikos Chrysos,
Giorgos Dimitrakopoulos:
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation.
Hot Interconnects 2008: 67-74 |
13 | EE | Giorgos Dimitrakopoulos,
Nikos Chrysos,
Costas Galanopoulos:
Fast arbiters for on-chip network switches.
ICCD 2008: 664-670 |
12 | EE | Giorgos Dimitrakopoulos,
Costas Galanopoulos,
Christos Mavrokefalidis,
Dimitris Nikolos:
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units.
IEEE Trans. VLSI Syst. 16(7): 837-850 (2008) |
2007 |
11 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
Costas Galanopoulos,
Dimitris Nikolos:
Sorter Based Permutation Units for Media-Enhanced Microprocessors.
IEEE Trans. VLSI Syst. 15(6): 711-715 (2007) |
2006 |
10 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
Costas Galanopoulos,
Dimitris Nikolos:
An Energy-Delay Efficient Subword Permutation Unit.
ASAP 2006: 245-252 |
9 | EE | Giorgos Dimitrakopoulos,
Christos Mavrokefalidis,
Costas Galanopoulos,
Dimitris Nikolos:
Fast bit permutation unit for media enhanced microprocessors.
ISCAS 2006 |
2005 |
8 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos:
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.
PATMOS 2005: 308-317 |
7 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos:
High-Speed Parallel-Prefix VLSI Ling Adders.
IEEE Trans. Computers 54(2): 225-231 (2005) |
6 | EE | Costas Efstathiou,
Haridimos T. Vergos,
Giorgos Dimitrakopoulos,
Dimitris Nikolos:
Efficient Diminished-1 Modulo 2^n+1 Multipliers.
IEEE Trans. Computers 54(4): 491-496 (2005) |
2004 |
5 | EE | Giorgos Dimitrakopoulos,
P. Kolovos,
P. Kalogerakis,
Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.
PATMOS 2004: 248-257 |
2003 |
4 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A Family of Parallel-Pre.x Modulo 2n - 1 Adders.
ASAP 2003: 326-336 |
3 | EE | Giorgos Dimitrakopoulos,
Haridimos T. Vergos,
Dimitris Nikolos,
Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders.
ISCAS (5) 2003: 225-228 |
2 | EE | Giorgos Dimitrakopoulos,
Xrysovalantis Kavousianos,
Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors.
ISCAS (5) 2003: 237-240 |
2002 |
1 | EE | Giorgos Dimitrakopoulos,
Dimitris Nikolos,
Dimitris Bakalis:
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.
IOLTW 2002: 152-157 |