2008 | ||
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19 | EE | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De: Analytical Model for the Propagation Delay of Through Silicon Vias. ISQED 2008: 553-556 |
18 | EE | Hao Yu, Yiyu Shi, Lei He, Tanay Karnik: Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. VLSI Syst. 16(12): 1609-1619 (2008) |
17 | EE | D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, V. K. De: Accurate Estimation of SRAM Dynamic Stability. IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008) |
2007 | ||
16 | EE | Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik: Low Voltage Buffered Bandgap Reference. ISQED 2007: 93-97 |
2006 | ||
15 | EE | Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner: High-frequency DC-DC conversion : fact or fiction. ISCAS 2006 |
14 | EE | Hao Yu, Yiyu Shi, Lei He, Tanay Karnik: Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED 2006: 156-161 |
13 | EE | Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik: Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED 2006: 326-329 |
12 | EE | Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7 |
2005 | ||
11 | EE | Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang: Logic soft errors in sub-65nm technologies design and CAD challenges. DAC 2005: 2-4 |
10 | EE | Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4 |
2004 | ||
9 | EE | Shekhar Borkar, Tanay Karnik, Vivek De: Design and reliability challenges in nanometer technologies. DAC 2004: 75 |
8 | EE | Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik: HiSIM: hierarchical interconnect-centric circuit simulator. ICCAD 2004: 489-496 |
7 | EE | Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva Narendra, Tanay Karnik, Vivek De: Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. ISLPED 2004: 263-268 |
6 | EE | Tanay Karnik, Peter Hazucha, Jagdish Patel: Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. IEEE Trans. Dependable Sec. Comput. 1(2): 128-143 (2004) |
2003 | ||
5 | EE | Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De: Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 |
2002 | ||
4 | EE | Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar: Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 |
3 | EE | Tanay Karnik, Shekhar Borkar, Vivek De: Sub-90nm technologies: challenges and opportunities for CAD. ICCAD 2002: 203-206 |
1995 | ||
2 | EE | Tanay Karnik, Sung-Mo Kang: An empirical model for accurate estimation of routing delay in FPGAs. ICCAD 1995: 328-331 |
1994 | ||
1 | EE | Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab: Structural and behavioral synthesis for testability techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 777-785 (1994) |