| |
| 2008 | ||
|---|---|---|
| 7 | EE | Paul Beckett: A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors. IEEE Trans. VLSI Syst. 16(2): 115-123 (2008) |
| 2007 | ||
| 6 | EE | Lianlian Zeng, Paul Beckett: Soft Error Rate Estimation in Deep Sub-micron CMOS. PRDC 2007: 210-216 |
| 2005 | ||
| 5 | EE | Paul Beckett: Low-power circuits using dynamic threshold devices. ACM Great Lakes Symposium on VLSI 2005: 213-216 |
| 4 | EE | Paul Beckett, S. C. Goldstein: Why area might reduce power in nanoscale CMOS. ISCAS (3) 2005: 2329-2332 |
| 3 | EE | Paul Beckett: Low-power spatial computing using dynamic threshold devices. ISCAS (3) 2005: 2345-2348 |
| 2003 | ||
| 2 | EE | Paul Beckett: Exploiting multiple functionality for nano-scale reconfigurable systems. ACM Great Lakes Symposium on VLSI 2003: 50-55 |
| 1 | EE | Paul Beckett: A Polymorphic Hardware Platform. IPDPS 2003: 175 |
| 1 | S. C. Goldstein | [4] |
| 2 | Lianlian Zeng | [6] |