dblp.uni-trier.dewww.uni-trier.de

Yasuhiro Morita

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
10EEHidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102
9EEHidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008)
8EEHiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008)
2007
7EEHiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112
6EEYasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Transactions 90-A(12): 2695-2702 (2007)
5EEYasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions 90-C(10): 1949-1956 (2007)
2006
4EEHidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
3EEToshiyuki Miyamoto, Yasuhiro Morita, Sadatoshi Kumagai: Vertical Partitioning Method for Secret Sharing Distributed Database System. IEICE Transactions 89-A(11): 3244-3249 (2006)
2EEYasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006)
2005
1EEKentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto: Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Transactions 88-A(12): 3290-3297 (2005)

Coauthor Index

1Hidehiro Fujiwara [2] [4] [5] [6] [7] [8] [9] [10]
2Yusuke Iguchi [5] [6] [7] [8] [10]
3Miwako Kanamori [1]
4Hiroshi Kawaguchi [2] [4] [5] [6] [7] [8] [9] [10]
5Kentaro Kawakami [1] [2]
6Sadatoshi Kumagai [3]
7Shinji Mikami [2]
8Junichi Miyakoshi [2] [4] [9]
9Masayuki Miyama [1]
10Toshiyuki Miyamoto [3]
11Yuichiro Murachi [4] [9]
12Koji Nii [2] [4] [5] [6] [7] [8] [9]
13Hiroki Noguchi [2] [5] [6] [7] [8] [9] [10]
14Shunsuke Okumura [8] [10]
15Jun Takemura [1]
16Masahiko Yoshimoto [1] [2] [4] [5] [6] [7] [8] [9] [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)