| 2008 |
|---|
| 148 | EE | Kevin T. Lim,
Parthasarathy Ranganathan,
Jichuan Chang,
Chandrakant D. Patel,
Trevor N. Mudge,
Steven K. Reinhardt:
Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments.
ISCA 2008: 315-326 |
| 147 | EE | Taeho Kgil,
David Roberts,
Trevor N. Mudge:
Improving NAND Flash Based Disk Caches.
ISCA 2008: 327-338 |
| 146 | EE | Ali G. Saidi,
Nathan L. Binkert,
Steven K. Reinhardt,
Trevor N. Mudge:
Full-System Critical Path Analysis.
ISPASS 2008: 63-74 |
| 145 | EE | Mark Woh,
Yuan Lin,
Sangwon Seo,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Richard Bruce,
Danny Kershaw,
Alastair Reid,
Mladen Wilder,
Krisztián Flautner:
From SODA to scotch: The evolution of a wireless baseband processor.
MICRO 2008: 152-163 |
| 144 | EE | Ronald G. Dreslinski,
Gregory K. Chen,
Trevor N. Mudge,
David Blaauw,
Dennis Sylvester,
Krisztián Flautner:
Reconfigurable energy efficient near threshold cache architectures.
MICRO 2008: 459-470 |
| 143 | EE | Emre Özer,
Ronald G. Dreslinski,
Trevor N. Mudge,
Stuart Biles,
Krisztián Flautner:
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.
SAMOS 2008: 12-22 |
| 142 | EE | Eric Karl,
David Blaauw,
Dennis Sylvester,
Trevor N. Mudge:
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems.
IEEE Trans. VLSI Syst. 16(4): 476-487 (2008) |
| 141 | EE | Taeho Kgil,
Ali G. Saidi,
Nathan L. Binkert,
Steven K. Reinhardt,
Krisztián Flautner,
Trevor N. Mudge:
PicoServer: Using 3D stacking technology to build energy efficient servers.
JETC 4(4): (2008) |
| 140 | EE | David Roberts,
Nam Sung Kim,
Trevor N. Mudge:
On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 244-253 (2008) |
| 2007 |
|---|
| 139 | EE | Yuan Lin,
Manjunath Kudlur,
Scott A. Mahlke,
Trevor N. Mudge:
Hierarchical coarse-grained stream compilation for software defined radio.
CASES 2007: 115-124 |
| 138 | EE | Trevor N. Mudge:
Multicore architectures.
CASES 2007: 208 |
| 137 | EE | Ronald G. Dreslinski,
Ali G. Saidi,
Trevor N. Mudge,
Steven K. Reinhardt:
Analysis of hardware prefetching across virtual page boundaries.
Conf. Computing Frontiers 2007: 13-22 |
| 136 | EE | David Roberts,
Nam Sung Kim,
Trevor N. Mudge:
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology.
DSD 2007: 570-578 |
| 135 | EE | Gregory K. Chen,
David Blaauw,
Trevor N. Mudge,
Dennis Sylvester,
Nam Sung Kim:
Yield-driven near-threshold SRAM design.
ICCAD 2007: 660-666 |
| 134 | EE | Bo Zhai,
Ronald G. Dreslinski,
David Blaauw,
Trevor N. Mudge,
Dennis Sylvester:
Energy efficient near-threshold chip multi-processing.
ISLPED 2007: 32-37 |
| 133 | EE | Ronald G. Dreslinski,
Bo Zhai,
Trevor N. Mudge,
David Blaauw,
Dennis Sylvester:
An Energy Efficient Parallel Architecture Using Near Threshold Operation.
PACT 2007: 175-188 |
| 132 | EE | Mark Woh,
Sangwon Seo,
Hyunseok Lee,
Yuan Lin,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
The Next Generation Challenge for Software Defined Radio.
SAMOS 2007: 343-354 |
| 131 | EE | Himanshu Kaul,
Dennis Sylvester,
David Blaauw,
Trevor N. Mudge,
Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction
CoRR abs/0710.4679: (2007) |
| 130 | EE | Robert Bai,
Nam Sung Kim,
Taeho Kgil,
Dennis Sylvester,
Trevor N. Mudge:
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage
CoRR abs/0710.4794: (2007) |
| 129 | EE | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A High-Performance DSP Architecture for Software-Defined Radio.
IEEE Micro 27(1): 114-123 (2007) |
| 2006 |
|---|
| 128 | EE | Taeho Kgil,
Shaun D'Souza,
Ali G. Saidi,
Nathan L. Binkert,
Ronald G. Dreslinski,
Trevor N. Mudge,
Steven K. Reinhardt,
Krisztián Flautner:
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.
ASPLOS 2006: 117-128 |
| 127 | EE | Taeho Kgil,
Trevor N. Mudge:
FlashCache: a NAND flash memory file cache for low power web servers.
CASES 2006: 103-112 |
| 126 | EE | Eric Karl,
David Blaauw,
Dennis Sylvester,
Trevor N. Mudge:
Reliability modeling and management in dynamic microprocessor-based systems.
DAC 2006: 1057-1060 |
| 125 | EE | Yuan Lin,
Hyunseok Lee,
Mark Woh,
Yoav Harel,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Krisztián Flautner:
SODA: A Low-power Architecture For Software Radio.
ISCA 2006: 89-101 |
| 124 | EE | Hyunseok Lee,
Trevor N. Mudge,
Chaitali Chakrabarti:
Reducing idle mode power in software defined radio terminals.
ISLPED 2006: 101-106 |
| 123 | EE | Ahmed Amine Jerraya,
Trevor N. Mudge:
Guest editorial: Concurrent hardware and software design for multiprocessor SoC.
ACM Trans. Embedded Comput. Syst. 5(2): 259-262 (2006) |
| 2005 |
|---|
| 122 | EE | Robert Bai,
Nam Sung Kim,
Dennis Sylvester,
Trevor N. Mudge:
Total leakage optimization strategies for multi-level caches.
ACM Great Lakes Symposium on VLSI 2005: 381-384 |
| 121 | EE | Todd M. Austin,
Valeria Bertacco,
David Blaauw,
Trevor N. Mudge:
Opportunities and challenges for better than worst-case design.
ASP-DAC 2005: 2-7 |
| 120 | EE | Hyunseok Lee,
Trevor N. Mudge:
A dual-processor solution for the MAC layer of a software defined radio terminal.
CASES 2005: 257-265 |
| 119 | EE | Trevor N. Mudge:
Performance and power analysis of computer systems.
CODES+ISSS 2005: 2 |
| 118 | EE | Janos Sztipanovits,
C. John Glossner,
Trevor N. Mudge,
Chris Rowen,
Alberto L. Sangiovanni-Vincentelli,
Wayne Wolf,
Feng Zhao:
Grand challenges in embedded systems.
CODES+ISSS 2005: 333 |
| 117 | EE | Robert Bai,
Nam Sung Kim,
Taeho Kgil,
Dennis Sylvester,
Trevor N. Mudge:
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage.
DATE 2005: 650-651 |
| 116 | EE | Himanshu Kaul,
Dennis Sylvester,
David Blaauw,
Trevor N. Mudge,
Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction.
DATE 2005: 80-85 |
| 115 | EE | Hyunseok Lee,
Yuan Lin,
Yoav Harel,
Mark Woh,
Scott A. Mahlke,
Trevor N. Mudge,
Krisztián Flautner:
Software Defined Radio - A High Performance Embedded Challenge.
HiPEAC 2005: 6-26 |
| 114 | EE | Weidong Shi,
Hsien-Hsin S. Lee,
Guofei Gu,
Laura Falk,
Trevor N. Mudge,
Mrinmoy Ghosh:
An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor.
ICAC 2005: 263-273 |
| 113 | | Peter Suaris,
Taeho Kgil,
Keith A. Bowman,
Vivek De,
Trevor N. Mudge:
Total power-optimal pipelining and parallel processing under process variations in nanometer technology.
ICCAD 2005: 535-540 |
| 112 | EE | Allen C. Cheng,
Gary S. Tyson,
Trevor N. Mudge:
PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis.
ISPASS 2005: 32-41 |
| 111 | EE | Jeff Ringenberg,
Chris Pelosi,
David W. Oehmke,
Trevor N. Mudge:
Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary Modification.
ISPASS 2005: 78-88 |
| 110 | EE | David Roberts,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge,
Krisztián Flautner:
Error Analysis for the Support of Robust Voltage Scaling.
ISQED 2005: 65-70 |
| 109 | EE | David W. Oehmke,
Nathan L. Binkert,
Trevor N. Mudge,
Steven K. Reinhardt:
How to Fake 1000 Registers.
MICRO 2005: 7-18 |
| 108 | EE | Trevor N. Mudge:
Introduction to the Special Section on Energy Efficient Computing.
IEEE Trans. Computers 54(6): 641- (2005) |
| 107 | EE | Nam Sung Kim,
David Blaauw,
Trevor N. Mudge:
Quantitative analysis and optimization techniques for on-chip cache leakage power.
IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005) |
| 106 | EE | Taeho Kgil,
Laura Falk,
Trevor N. Mudge:
ChipLock: support for secure microarchitectures.
SIGARCH Computer Architecture News 33(1): 134-143 (2005) |
| 2004 |
|---|
| 105 | EE | Seokwoo Lee,
Shidhartha Das,
Valeria Bertacco,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge:
Circuit-aware architectural simulation.
DAC 2004: 305-310 |
| 104 | EE | Allen C. Cheng,
Gary S. Tyson,
Trevor N. Mudge:
FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.
DAC 2004: 920-923 |
| 103 | EE | Trevor N. Mudge:
Low Power Robust Computing.
HiPC 2004: 6 |
| 102 | EE | Nam Sung Kim,
Taeho Kgil,
Valeria Bertacco,
Todd M. Austin,
Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors.
ISLPED 2004: 212-217 |
| 101 | EE | Seokwoo Lee,
Shidhartha Das,
Toan Pham,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge:
Reducing pipeline energy demands with local DVS and dynamic retiming.
ISLPED 2004: 319-324 |
| 100 | EE | Todd M. Austin,
David Blaauw,
Trevor N. Mudge,
Krisztián Flautner:
Making Typical Silicon Matter with Razor.
IEEE Computer 37(3): 57-65 (2004) |
| 99 | EE | Todd M. Austin,
David Blaauw,
Scott A. Mahlke,
Trevor N. Mudge,
Chaitali Chakrabarti,
Wayne Wolf:
Mobile Supercomputers.
IEEE Computer 37(5): 81-83 (2004) |
| 98 | EE | Dan Ernst,
Shidhartha Das,
Seokwoo Lee,
David Blaauw,
Todd M. Austin,
Trevor N. Mudge,
Nam Sung Kim,
Krisztián Flautner:
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation.
IEEE Micro 24(6): 10-20 (2004) |
| 97 | | Nam Sung Kim,
Krisztián Flautner,
David Blaauw,
Trevor N. Mudge:
Circuit and microarchitectural techniques for reducing cache leakage power.
IEEE Trans. VLSI Syst. 12(2): 167-184 (2004) |
| 2003 |
|---|
| 96 | EE | Nam Sung Kim,
David Blaauw,
Trevor N. Mudge:
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches.
ICCAD 2003: 627-632 |
| 95 | EE | Nam Sung Kim,
Trevor N. Mudge:
Reducing register ports using delayed write-back queues and operand pre-fetch.
ICS 2003: 172-182 |
| 94 | EE | Nam Sung Kim,
Trevor N. Mudge:
The microarchitecture of a low power register file.
ISLPED 2003: 384-389 |
| 93 | EE | Dan Ernst,
Nam Sung Kim,
Shidhartha Das,
Sanjay Pant,
Rajeev R. Rao,
Toan Pham,
Conrad H. Ziesler,
David Blaauw,
Todd M. Austin,
Krisztián Flautner,
Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
MICRO 2003: 7-18 |
| 92 | EE | Guang R. Gao,
Trevor N. Mudge:
Special issue on compilers, architecture, and synthesis for embedded systems.
ACM Trans. Embedded Comput. Syst. 2(2): 131 (2003) |
| 91 | EE | Nam Sung Kim,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge,
Krisztián Flautner,
Jie S. Hu,
Mary Jane Irwin,
Mahmut T. Kandemir,
Narayanan Vijaykrishnan:
Leakage Current: Moore's Law Meets Static Power.
IEEE Computer 36(12): 68-75 (2003) |
| 2002 |
|---|
| 90 | | Shuvra S. Bhattacharyya,
Trevor N. Mudge,
Wayne Wolf,
Ahmed Amine Jerraya:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002
ACM 2002 |
| 89 | EE | Steven M. Martin,
Krisztián Flautner,
Trevor N. Mudge,
David Blaauw:
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
ICCAD 2002: 721-725 |
| 88 | EE | Krisztián Flautner,
Nam Sung Kim,
Steven M. Martin,
David Blaauw,
Trevor N. Mudge:
Drowsy Caches: Simple Techniques for Reducing Leakage Power.
ISCA 2002: 148-157 |
| 87 | EE | Nam Sung Kim,
Krisztián Flautner,
David Blaauw,
Trevor N. Mudge:
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.
MICRO 2002: 219-230 |
| 86 | EE | Krisztián Flautner,
Trevor N. Mudge:
Vertigo: Automatic Performance-Setting for Linux.
OSDI 2002 |
| 85 | EE | David Blaauw,
Steven M. Martin,
Trevor N. Mudge,
Krisztián Flautner:
Leakage Current Reduction in VLSI Systems.
Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002) |
| 2001 |
|---|
| 84 | EE | Matt Postiff,
David Greene,
Steven E. Raasch,
Trevor N. Mudge:
Integrating superscalar processor components to implement register caching.
ICS 2001: 348-357 |
| 83 | EE | Krisztián Flautner,
Steven K. Reinhardt,
Trevor N. Mudge:
Automatic performance setting for dynamic voltage scaling.
MOBICOM 2001: 260-271 |
| 82 | EE | Trevor N. Mudge:
Power: A First-Class Architectural Design Constraint.
IEEE Computer 34(4): 52-58 (2001) |
| 81 | EE | Vinodh Cuppu,
Bruce L. Jacob,
Brian Davis,
Trevor N. Mudge:
High-Performance DRAMs in Workstation Environments.
IEEE Trans. Computers 50(11): 1133-1153 (2001) |
| 80 | EE | Bruce L. Jacob,
Trevor N. Mudge:
Uniprocessor Virtual Memory without TLBs.
IEEE Trans. Computers 50(5): 482-499 (2001) |
| 2000 |
|---|
| 79 | EE | Krisztián Flautner,
Richard Uhlig,
Steven K. Reinhardt,
Trevor N. Mudge:
Thread Level Parallelism and Interactive Performance of Desktop Applications.
ASPLOS 2000: 129-138 |
| 78 | EE | Charles Lefurgy,
Eva Piccininni,
Trevor N. Mudge:
Reducing Code Size with Run-Time Decompression.
HPCA 2000: 218- |
| 77 | EE | Trevor N. Mudge:
Power: A First Class Design Constraint for Future Architecture and Automation.
HiPC 2000: 215-224 |
| 76 | EE | Brian Davis,
Bruce L. Jacob,
Trevor N. Mudge:
The New DRAM Interfaces: SDRAM, RDRAM and Variants.
ISHPC 2000: 26-31 |
| 75 | EE | Matt Postiff,
David Greene,
Trevor N. Mudge:
The store-load address table and speculative register promotion.
MICRO 2000: 235-244 |
| 74 | EE | Richard Uhlig,
Trevor N. Mudge:
Trace-Driven Memory Simulation: A Survey.
Performance Evaluation 2000: 97-139 |
| 73 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
Collection and Analysis of Microprocessor Design Errors.
IEEE Design & Test of Computers 17(4): 51-60 (2000) |
| 1999 |
|---|
| 72 | EE | David Van Campenhout,
Trevor N. Mudge,
John P. Hayes:
High-Level Test Generation for Design Verification of Pipelined Microprocessors.
DAC 1999: 185-188 |
| 71 | EE | Vinodh Cuppu,
Bruce L. Jacob,
Brian Davis,
Trevor N. Mudge:
A Performance Comparison of Contemporary DRAM Architectures.
ISCA 1999: 222-233 |
| 70 | EE | Charles Lefurgy,
Eva Piccininni,
Trevor N. Mudge:
Evaluation of a High Performance Code Compression Method.
MICRO 1999: 93-102 |
| 69 | EE | David Van Campenhout,
Trevor N. Mudge,
Karem A. Sakallah:
Timing verification of sequential dynamic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 645-658 (1999) |
| 68 | EE | Matt Postiff,
Gary S. Tyson,
Trevor N. Mudge:
Performance Limits of Trace Caches.
J. Instruction-Level Parallelism 1: (1999) |
| 1998 |
|---|
| 67 | EE | Bruce L. Jacob,
Trevor N. Mudge:
A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations.
ASPLOS 1998: 295-306 |
| 66 | EE | A. N. Eden,
Trevor N. Mudge:
The YAGS Branch Prediction Scheme.
MICRO 1998: 69-77 |
| 65 | EE | David Van Campenhout,
Hussain Al-Asaad,
John P. Hayes,
Trevor N. Mudge,
Richard B. Brown:
High-level design verification of microprocessors via error modeling.
ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998) |
| 64 | | Bruce L. Jacob,
Trevor N. Mudge:
Virtual Memory: Issues of Implementation.
IEEE Computer 31(6): 33-43 (1998) |
| 63 | EE | Richard B. Brown,
Bruce Bernhardt,
M. LaMacchia,
J. Abrokwah,
Phiroze N. Parakh,
Todd D. Basso,
Spencer M. Gold,
S. Stetson,
Claude R. Gauthier,
D. Foster,
B. Crawforth,
T. McQuire,
Karem A. Sakallah,
Ronald J. Lomax,
Trevor N. Mudge:
Overview of complementary GaAs technology for high-speed VLSI circuits.
IEEE Trans. VLSI Syst. 6(1): 47-51 (1998) |
| 1997 |
|---|
| 62 | EE | Bruce L. Jacob,
Trevor N. Mudge:
Software-Managed Address Translation.
HPCA 1997: 156-167 |
| 61 | | I-Cheng K. Chen,
Chih-Chieh Lee,
Trevor N. Mudge:
Instruction Prefetching Using Branch Prediction Information.
ICCD 1997: 593-601 |
| 60 | | I-Cheng K. Chen,
Chih-Chieh Lee,
Matt Postiff,
Trevor N. Mudge:
Design Optimization for High-speed Per-address Two-level Branch Predictors.
ICCD 1997: 88-96 |
| 59 | EE | James Dundas,
Trevor N. Mudge:
Improving Data Cache Performance by Pre-Executing Instructions Under a Cache Miss.
International Conference on Supercomputing 1997: 68-75 |
| 58 | EE | Charles Lefurgy,
Peter L. Bird,
I-Cheng K. Chen,
Trevor N. Mudge:
Improving Code Density Using Compression Techniques.
MICRO 1997: 194-203 |
| 57 | EE | Chih-Chieh Lee,
I-Cheng K. Chen,
Trevor N. Mudge:
The bi-Mode Branch Predictor.
MICRO 1997: 4-13 |
| 56 | EE | Richard Uhlig,
Trevor N. Mudge:
Trace-Driven Memory Simulation: A Survey.
ACM Comput. Surv. 29(2): 128-170 (1997) |
| 55 | EE | Richard Uhlig,
David Nagle,
Trevor N. Mudge,
Stuart Sechrest:
Trap-Driven Memory Simulation with Tapeworm II.
ACM Trans. Model. Comput. Simul. 7(1): 7-41 (1997) |
| 54 | | Kunle Olukotun,
Trevor N. Mudge,
Richard B. Brown:
Multilevel Optimization of Pipelined Caches.
IEEE Trans. Computers 46(10): 1083-1102 (1997) |
| 53 | | Bruce L. Jacob,
Peter M. Chen,
Seth R. Silverman,
Trevor N. Mudge:
A Comment on ``An Analytical Model for Designing Memory Hierarchies''.
IEEE Trans. Computers 46(10): 1151 (1997) |
| 1996 |
|---|
| 52 | EE | Bruce L. Jacob,
Trevor N. Mudge:
The trading function in action.
ACM SIGOPS European Workshop 1996: 241-247 |
| 51 | | I-Cheng K. Chen,
John T. Coffey,
Trevor N. Mudge:
Analysis of Branch Prediction Via Data Compression.
ASPLOS 1996: 128-137 |
| 50 | EE | David Van Campenhout,
Trevor N. Mudge,
Karem A. Sakallah:
Timing verification of sequential domino circuits.
ICCAD 1996: 127-132 |
| 49 | EE | Stuart Sechrest,
Chih-Chieh Lee,
Trevor N. Mudge:
Correlation and Aliasing in Dynamic Branch Predictors.
ISCA 1996: 22-32 |
| 48 | EE | Jim Pierce,
Trevor N. Mudge:
Wrong-path Instruction Prefetching.
MICRO 1996: 165-175 |
| 47 | | Trevor N. Mudge:
Strategic Directions in Computer Architecture.
ACM Comput. Surv. 28(4): 671-678 (1996) |
| 46 | | Bruce L. Jacob,
Peter M. Chen,
Seth R. Silverman,
Trevor N. Mudge:
An Analytical Model for Designing Memory Hierarchies.
IEEE Trans. Computers 45(10): 1180-1194 (1996) |
| 1995 |
|---|
| 45 | EE | Timothy J. Stanley,
Trevor N. Mudge:
Systematic objective-driven computer architecture optimization.
ARVLSI 1995: 286-303 |
| 44 | | Timothy J. Stanley,
Trevor N. Mudge:
A Parallel Genetic Algorithm for Multiobjective Microprocessor Design.
ICGA 1995: 597-604 |
| 43 | EE | Richard Uhlig,
David Nagle,
Trevor N. Mudge,
Stuart Sechrest,
Joel S. Emer:
Instruction Fetching: Coping with Code Bloat.
ISCA 1995: 345-356 |
| 42 | EE | Stuart Sechrest,
Chih-Chieh Lee,
Trevor N. Mudge:
The role of adaptivity in two-level adaptive branch prediction.
MICRO 1995: 264-269 |
| 41 | EE | Timothy M. Burks,
Karem A. Sakallah,
Trevor N. Mudge:
Critical paths in circuits with level-sensitive latches.
IEEE Trans. VLSI Syst. 3(2): 273-291 (1995) |
| 1994 |
|---|
| 40 | | Richard Uhlig,
David Nagle,
Trevor N. Mudge,
Stuart Sechrest:
Trap-driven Simulation with Tapeworm II.
ASPLOS 1994: 132-144 |
| 39 | | Michael Upton,
Thomas Huff,
Trevor N. Mudge,
Richard B. Brown:
Resource Allocation in a High Clock Rate Microprocessor.
ASPLOS 1994: 98-109 |
| 38 | | Jim Pierce,
Trevor N. Mudge:
The Effect of Speculative Execution on Cache Performance.
IPPS 1994: 172-179 |
| 37 | | David Nagle,
Richard Uhlig,
Trevor N. Mudge,
Stuart Sechrest:
Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems.
ISCA 1994: 358-369 |
| 36 | | Jim Pierce,
Trevor N. Mudge:
IDtrace - A Tracing Tool for i486 Simulation.
MASCOTS 1994: 419-420 |
| 35 | EE | Michael Golden,
Trevor N. Mudge:
A comparison of two pipeline organizations.
MICRO 1994: 153-161 |
| 34 | | Richard Uhlig,
David Nagle,
Trevor N. Mudge,
Stuart Sechrest:
Kernel-Based Memory Simulation.
SIGMETRICS 1994: 286-287 |
| 33 | EE | Richard Uhlig,
David Nagle,
Timothy J. Stanley,
Trevor N. Mudge,
Stuart Sechrest,
Richard B. Brown:
Design Tradeoffs for Software-Managed TLBs.
ACM Trans. Comput. Syst. 12(3): 175-205 (1994) |
| 1993 |
|---|
| 32 | | David Nagle,
Richard Uhlig,
Timothy J. Stanley,
Stuart Sechrest,
Trevor N. Mudge,
Richard B. Brown:
Design Tradeoffs for Software-Managed TLBs.
ISCA 1993: 27-38 |
| 31 | EE | Timothy J. Stanley,
Michael Upton,
Patrick Sherhart,
Trevor N. Mudge,
Richard B. Brown:
A microarchitectural performance evaluation of a 3.2 Gbyte/s microprocessor bus.
MICRO 1993: 31-40 |
| 30 | EE | Karem A. Sakallah,
Trevor N. Mudge,
Timothy M. Burks,
Edward S. Davidson:
Synchronization of pipelines.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1132-1146 (1993) |
| 1992 |
|---|
| 29 | EE | Timothy M. Burks,
Karem A. Sakallah,
Trevor N. Mudge:
Identification of critical paths in circuits with level-sensitive latches.
ICCAD 1992: 137-141 |
| 28 | | Kunle Olukotun,
Trevor N. Mudge,
Richard B. Brown:
Performance Optimization of Pipelined Primary Caches.
ISCA 1992: 181-190 |
| 27 | EE | Karem A. Sakallah,
Trevor N. Mudge,
Oyekunle A. Olukotun:
Analysis and design of latch-controlled synchronous digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 322-333 (1992) |
| 1991 |
|---|
| 26 | | Karem A. Sakallah,
Trevor N. Mudge,
Timothy M. Burks,
Edward S. Davidson:
Optimal Clocking of Circular Pipelines.
ICCD 1991: 642-650 |
| 25 | EE | Kunle Olukotun,
Trevor N. Mudge,
Richard B. Brown:
Implementing a Cache for a High-Performance GaAs Microprocessor.
ISCA 1991: 138-147 |
| 24 | | Trevor N. Mudge,
Richard B. Brown,
William P. Bimingham,
Jeffrey A. Dykstra,
Ayman I. Kayssi,
Ronald J. Lomax,
Kunle Olukotun,
Karem A. Sakallah,
Raymond A. Milano:
The Design of a Microsupercomputer.
IEEE Computer 24(1): 57-64 (1991) |
| 1990 |
|---|
| 23 | EE | Karem A. Sakallah,
Trevor N. Mudge,
Kunle Olukotun:
Analysis and Design of Latch-Controlled Synchronous Digital Circuits.
DAC 1990: 111-117 |
| 22 | | Karem A. Sakallah,
Trevor N. Mudge,
Kunle Olukotun:
check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits.
ICCAD 1990: 552-555 |
| 21 | | Oyekunle A. Olukotun,
Trevor N. Mudge:
Hierarchical Gate-Array Routing on a Hypercube Multiprocessor.
J. Parallel Distrib. Comput. 8(4): 313-324 (1990) |
| 1989 |
|---|
| 20 | | Paul G. Gottschalk,
Jerry L. Turney,
Trevor N. Mudge:
Efficient Recognition of Partially Visible Objects Using a Logarithmic Complexity Matching Technique.
I. J. Robotic Res. 8(6): 110-131 (1989) |
| 19 | EE | Richard A. Volz,
Trevor N. Mudge,
Gregory D. Buzzard,
Padmanabhan Krishnan:
Translation and Execution of Distributed Ada Programs: Is It Still Ada?
IEEE Trans. Software Eng. 15(3): 281-292 (1989) |
| 1988 |
|---|
| 18 | | Donald C. Winsor,
Trevor N. Mudge:
Analysis of Bus Hierarchies for Multiprocessors.
ISCA 1988: 100-107 |
| 1987 |
|---|
| 17 | EE | Kunle Olukotun,
Trevor N. Mudge:
A Preliminary Investigation into Parallel Routing on a Hypercube Computer.
DAC 1987: 814-820 |
| 16 | | Donald C. Winsor,
Trevor N. Mudge:
Crosspoint Cache Architectures.
ICPP 1987: 266-269 |
| 15 | | Richard A. Volz,
Trevor N. Mudge:
Timing Issues in the Distributed Execution of Ada Programs.
IEEE Trans. Computers 36(4): 449-459 (1987) |
| 14 | | Richard A. Volz,
Trevor N. Mudge:
Instruction Level Timing Mechanisms for Accurate Real-Time Task Scheduling.
IEEE Trans. Computers 36(8): 988-993 (1987) |
| 13 | | Trevor N. Mudge,
T. S. Abdel-Rahman:
Vision Algorithms for Hypercube Machines.
J. Parallel Distrib. Comput. 4(1): 79-94 (1987) |
| 1986 |
|---|
| 12 | | John P. Hayes,
Trevor N. Mudge,
Quentin F. Stout:
Architecture of a Hypercube Supercomputer.
ICPP 1986: 653-660 |
| 11 | | Richard A. Volz,
Trevor N. Mudge:
Instruction Level Mechanisms for Accurate Real-time Task Scheduling.
IEEE Real-Time Systems Symposium 1986: 209-215 |
| 10 | | Russell M. Clapp,
Louis Duchesneau,
Richard A. Volz,
Trevor N. Mudge,
Timothy Schultze:
Toward Real-Time Performance Benchmarks for Ada.
Commun. ACM 29(8): 760-778 (1986) |
| 9 | | Trevor N. Mudge,
John P. Hayes,
Gregory D. Buzzard,
Donald C. Winsor:
Analysis of Multiple-Bus Interconnection Networks.
J. Parallel Distrib. Comput. 3(3): 328-343 (1986) |
| 1985 |
|---|
| 8 | | Trevor N. Mudge,
Humoud B. Al-Sadoun:
A Semi-Markov Model for the Performance of Multiple-Bus Systems.
ICPP 1985: 521-530 |
| 7 | | Gregory D. Buzzard,
Trevor N. Mudge:
Object-Based Computing and the Ada Programming Language.
IEEE Computer 18(3): 11-19 (1985) |
| 6 | | Trevor N. Mudge,
Humoud B. Al-Sadoun:
A Semi-Markov Model for the Performance of Multiple-Bus Systems.
IEEE Trans. Computers 34(10): 934-942 (1985) |
| 1984 |
|---|
| 5 | | Trevor N. Mudge,
Humoud B. Al-Sadoun:
Memory Interference Models with Variable Connection Time.
IEEE Trans. Computers 33(11): 1033-1038 (1984) |
| 4 | EE | Rob A. Rutenbar,
Trevor N. Mudge,
Daniel E. Atkins:
A Class of Cellular Architectures to Support Physical Design Automation.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(4): 264-278 (1984) |
| 1983 |
|---|
| 3 | | Trevor N. Mudge,
Abdel-Rahman H. Tawil:
Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images.
ICPP 1983: 369-373 |
| 1982 |
|---|
| 2 | | Trevor N. Mudge,
B. A. Makrucki:
An Approximate Queueing Model for Packet Switched Multistage Interconnection Networks.
ICDCS 1982: 556-562 |
| 1 | EE | Trevor N. Mudge,
B. A. Makrucki:
Probabilistic analysis of a crossbar switch.
ISCA 1982: 311-320 |
