Avinoam Kolodny

2009
31	EE	Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman: Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290
2008
30	EE	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny: Timing optimization in logic with interconnect. SLIP 2008: 19-26
29	EE	Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar: Parallel vs. serial on-chip communication. SLIP 2008: 43-50
28	EE	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10
27	EE	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
26	EE	Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman: Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. VLSI Syst. 16(7): 894-907 (2008)
25	EE	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. VLSI Syst. 16(7): 908-921 (2008)
24	EE	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny: On optimal ordering of signals in parallel wire bundles. Integration 41(2): 253-268 (2008)
2007
23	EE	Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny: High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link. ASYNC 2007: 3-14
22	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Routing table minimization for irregular mesh NoCs. DATE 2007: 942-947
21	EE	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny: The Power of Priority: NoC Based Distributed Cache Coherency. NOCS 2007: 117-126
20	EE	Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Access Regulation to Hot-Modules in Wormhole NoCs. NOCS 2007: 137-148
19	EE	Avinoam Kolodny: Networks on chips: keeping up with Rent's rule and Moore's law. SLIP 2007: 55-56
18	EE	Michael Behar, Avi Mendelson, Avinoam Kolodny: Trace cache sampling filter. ACM Trans. Comput. Syst. 25(1): (2007)
17	EE	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser: Nahalal: Cache Organization for Chip Multiprocessors. Computer Architecture Letters 6(1): 21-24 (2007)
2006
16	EE	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu: Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179
15	EE	Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny: Fast Asynchronous Shift Register for Bit-Serial Communication. ASYNC 2006: 117-127
14	EE	Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Efficient link capacity and QoS design for network-on-chip. DATE 2006: 9-14
13	EE	Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman: On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006
12	EE	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny: Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006
11	EE	Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny: Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. VLSI Syst. 14(11): 1276-1281 (2006)
2005
10	EE	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny: On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7
9	EE	Michael Behar, Avi Mendelson, Avinoam Kolodny: Trace Cache Sampling Filter. IEEE PACT 2005: 255-266
8	EE	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Low-leakage repeaters for NoC interconnects. ISCAS (1) 2005: 600-603
7	EE	Noam Dolev, Avner Kornfeld, Avinoam Kolodny: Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology. Journal of Circuits, Systems, and Computers 14(3): 515-532 (2005)
2004
6	EE	Nir Magen, Avinoam Kolodny, Uri Weiser, Nachum Shamir: Interconnect-power dissipation in a microprocessor. SLIP 2004: 7-13
5	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: Cost considerations in network on chip. Integration 38(1): 19-42 (2004)
4	EE	Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny: QNoC: QoS architecture and design process for network on chip. Journal of Systems Architecture 50(2-3): 105-128 (2004)
2003
3		Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny: Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects. VLSI-SOC 2003: 99-104
2	EE	Y. Elboim, Avinoam Kolodny, Ran Ginosar: A clock-tuning circuit for system-on-chip. IEEE Trans. VLSI Syst. 11(4): 616-626 (2003)
1	EE	O. Milter, Avinoam Kolodny: Crosstalk noise reduction in synthesized digital logic circuits. IEEE Trans. VLSI Syst. 11(6): 1153-1158 (2003)

Coauthor Index

1	Michael Behar	[9] [18]
2	Evgeny Bolotin	[4] [5] [14] [21] [22]
3	Israel Cidon	[4] [5] [8] [14] [20] [21] [22]
4	Rostislav (Reuven) Dobkin	[15] [23] [29]
5	Noam Dolev	[7]
6	Y. Elboim	[2]
7	Eby G. Friedman	[10] [13] [16] [25] [26] [30] [31]
8	Ran Ginosar	[2] [4] [5] [8] [14] [15] [20] [21] [22] [23] [29] [30] [31]
9	Zvika Guz	[14] [17] [21] [28]
10	Idit Keidar	[17] [28]
11	Avner Kornfeld	[7]
12	Tuvia Liran	[23]
13	Nir Magen	[6]
14	Avi Mendelson	[9] [18]
15	O. Milter	[1]
16	Konstantin Moiseev	[12] [24] [27]
17	Michael Moreinis	[3] [11]
18	Arkadiy Morgenshtein	[3] [8] [11] [29] [30]
19	Yevgeny Perelman	[23]
20	Mikhail Popovich	[10] [13] [16] [25] [26]
21	Radu M. Secareanu	[16]
22	Nachum Shamir	[6]
23	Michael Sotman	[10] [13] [16] [25] [26]
24	Inna Vaisband	[31]
25	Israel A. Wagner	[3] [11]
26	Isask'har Walter	[14] [20]
27	Uri Weiser	[6]
28	Uri C. Weiser	[17] [28]
29	Shmuel Wimer	[12] [24] [27]

Colors in the list of coauthors