2009 |
30 | EE | Shunsuke Okumura,
Yusuke Iguchi,
Shusuke Yoshimoto,
Hidehiro Fujiwara,
Hiroki Noguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.
ISQED 2009: 659-663 |
29 | EE | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.
VLSI Design 2009: 295-300 |
2008 |
28 | EE | Yuichiro Murachi,
Kusuke Mizuno,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Tetsuya Kamino,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.
ISCAS 2008: 848-851 |
27 | EE | Hidehiro Fujiwara,
Shunsuke Okumura,
Yusuke Iguchi,
Hiroki Noguchi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Quality of a Bit (QoB): A New Concept in Dependable SRAM.
ISQED 2008: 98-102 |
26 | EE | Hidehiro Fujiwara,
Koji Nii,
Hiroki Noguchi,
Junichi Miyakoshi,
Yuichiro Murachi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering.
IEEE Trans. VLSI Syst. 16(6): 620-627 (2008) |
25 | EE | Yuichiro Murachi,
Yuki Fukuyama,
Ryo Yamamoto,
Junichi Miyakoshi,
Hiroshi Kawaguchi,
Hajime Ishihara,
Masayuki Miyama,
Yoshio Matsuda,
Masahiko Yoshimoto:
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.
IEICE Transactions 91-C(4): 457-464 (2008) |
24 | EE | Yuichiro Murachi,
Junichi Miyakoshi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Fang Yin,
Jangchung Lee,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.
IEICE Transactions 91-C(4): 465-478 (2008) |
23 | EE | Hiroki Noguchi,
Yusuke Iguchi,
Hidehiro Fujiwara,
Shunsuke Okumura,
Yasuhiro Morita,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.
IEICE Transactions 91-C(4): 543-552 (2008) |
2007 |
22 | EE | Kentaro Kawakami,
Mitsuhiko Kuroda,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture.
ASP-DAC 2007: 292-297 |
21 | EE | Hiroki Noguchi,
Yusuke Iguchi,
Hidehiro Fujiwara,
Yasuhiro Morita,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing.
ISVLSI 2007: 107-112 |
20 | EE | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Yusuke Iguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme.
IEICE Transactions 90-A(12): 2695-2702 (2007) |
19 | EE | Augusto Foronda,
Yuhi Higuchi,
Chikara Ohta,
Masahiko Yoshimoto,
Yoji Okada:
Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE 802.11e WLANs.
IEICE Transactions 90-B(11): 3158-3169 (2007) |
18 | EE | Takashi Matsuda,
Masumi Ichien,
Hiroshi Kawaguchi,
Chikara Ohta,
Masahiko Yoshimoto:
Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks.
IEICE Transactions 90-B(12): 3410-3418 (2007) |
17 | EE | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Yusuke Iguchi,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes.
IEICE Transactions 90-C(10): 1949-1956 (2007) |
2006 |
16 | EE | Takafumi Aonishi,
Takashi Matsuda,
Shinji Mikami,
Hiroshi Kawaguchi,
Chikara Ohta,
Masahiko Yoshimoto:
Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks.
ICPP Workshops 2006: 151-158 |
15 | EE | Hidehiro Fujiwara,
Koji Nii,
Junichi Miyakoshi,
Yuichiro Murachi,
Yasuhiro Morita,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering.
ISLPED 2006: 61-66 |
14 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto,
Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
VLSI-SoC 2006: 192-197 |
13 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Tetsuro Matsuno,
Masaki Hamamoto,
Takahiro Iinuma,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masayuki Miyama,
Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.
IEICE Transactions 89-A(12): 3623-3633 (2006) |
12 | EE | Yasuhiro Morita,
Hidehiro Fujiwara,
Hiroki Noguchi,
Kentaro Kawakami,
Junichi Miyakoshi,
Shinji Mikami,
Koji Nii,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond.
IEICE Transactions 89-A(12): 3634-3641 (2006) |
11 | EE | Kentaro Kawakami,
Jun Takemura,
Mitsuhiko Kuroda,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline.
IEICE Transactions 89-A(12): 3642-3651 (2006) |
10 | EE | Shinji Mikami,
Takafumi Aonishi,
Hironori Yoshino,
Chikara Ohta,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks.
IEICE Transactions 89-B(10): 2741-2751 (2006) |
9 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Tomokazu Ishihara,
Hiroshi Kawaguchi,
Masahiko Yoshimoto:
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.
IEICE Transactions 89-C(11): 1629-1636 (2006) |
8 | EE | Noriyuki Minegishi,
Junichi Miyakoshi,
Yuki Kuroda,
Tadayoshi Katagiri,
Yuki Fukuyama,
Ryo Yamamoto,
Masayuki Miyama,
Kousuke Imamura,
Hideo Hashimoto,
Masahiko Yoshimoto:
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation.
IEICE Transactions 89-C(3): 230-242 (2006) |
2005 |
7 | EE | Kentaro Kawakami,
Miwako Kanamori,
Yasuhiro Morita,
Jun Takemura,
Masayuki Miyama,
Masahiko Yoshimoto:
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era.
IEICE Transactions 88-A(12): 3290-3297 (2005) |
6 | EE | Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Junichi Miyakoshi,
Masayuki Miyama,
Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application.
IEICE Transactions 88-A(12): 3492-3499 (2005) |
5 | EE | Junichi Miyakoshi,
Yuichiro Murachi,
Koji Hamano,
Tetsuro Matsuno,
Masayuki Miyama,
Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation.
IEICE Transactions 88-C(4): 559-569 (2005) |
2004 |
4 | EE | Yuki Kuroda,
Junichi Miyakoshi,
Masayuki Miyama,
Kousuke Imamura,
Hideo Hashimoto,
Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application.
ASP-DAC 2004: 527-528 |
2003 |
3 | EE | Hideo Ohira,
Mitsuru Kodama,
Masahiko Yoshimoto:
The development and impact on business of the world's first live video streaming distribution platform for 3G mobile videophone terminals.
IJEB 1(1): 94-105 (2003) |
2 | EE | Hideo Ohira,
Mitsuru Kodama,
Masahiko Yoshimoto:
A world first development of a multipoint videophone system over 3G-324M protocol.
IJMC 1(3): 264-272 (2003) |
2001 |
1 | EE | A. Watanabe,
O. Tooyama,
Masayuki Miyama,
Masahiko Yoshimoto,
J. Akita:
An image sensor with fast extraction of objects' positions - rough vision processor.
ICIP (2) 2001: 1105-1108 |