| 2008 |
|---|
| 18 | EE | Yen-Jen Chang:
Exploiting frequent opcode locality for power efficient instruction cache.
ACM Great Lakes Symposium on VLSI 2008: 399-402 |
| 17 | EE | Yen-Jen Chang,
Yuan-Hong Liao:
Hybrid-Type CAM Design for Both Power and Performance Efficiency.
IEEE Trans. VLSI Syst. 16(8): 965-974 (2008) |
| 2007 |
|---|
| 16 | EE | Yen-Jen Chang,
Yuan-Hong Liao,
Shanq-Jang Ruan:
Improve CAM power efficiency using decoupled match line scheme.
DATE 2007: 165-170 |
| 15 | EE | Yen-Jen Chang,
Maofeng Lan:
Two New Techniques Integrated for Energy-Efficient TLB Design.
IEEE Trans. VLSI Syst. 15(1): 13-23 (2007) |
| 2006 |
|---|
| 14 | EE | Yen-Jen Chang:
Lazy BTB: reduce BTB energy consumption using dynamic profiling.
ASP-DAC 2006: 917-922 |
| 13 | EE | Yen-Jen Chang:
An ultra low-power TLB design.
DATE 2006: 1122-1127 |
| 12 | EE | Yen-Jen Chang:
An Alternative Real-Time Filter Scheme to Block Buffering.
VLSI Design 2006: 762-765 |
| 2005 |
|---|
| 11 | EE | Yen-Jen Chang,
Feipei Lai:
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.
IEEE Micro 25(4): 20-32 (2005) |
| 2004 |
|---|
| 10 | EE | Yen-Jen Chang,
Chia-Lin Yang,
Feipei Lai:
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.
DATE 2004: 16-21 |
| 9 | EE | Yen-Jen Chang,
Yung-Ching Weng,
Feipei Lai:
Enhanced object management for high performance web proxies.
SAC 2004: 1711-1716 |
| 8 | EE | Yen-Jen Chang,
Feipei Lai,
Chia-Lin Yang:
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
IEEE Trans. VLSI Syst. 12(8): 827-836 (2004) |
| 2003 |
|---|
| 7 | EE | Yen-Jen Chang,
Chia-Lin Yang,
Feipei Lai:
A power-aware SWDR cell for reducing cache write power.
ISLPED 2003: 14-17 |
| 6 | EE | Yen-Jen Chang,
Shanq-Jang Ruan,
Feipei Lai:
Design and analysis of low-power cache using two-level filter scheme.
IEEE Trans. VLSI Syst. 11(4): 568-580 (2003) |
| 2002 |
|---|
| 5 | EE | Yen-Jen Chang,
Feipei Lai:
Paged cache: an efficient partition architecture for reducing power, area and access time.
APCCAS (2) 2002: 473-478 |
| 4 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Yen-Jen Chang,
Chia-Lin Ho,
Feipei Lai:
Energy analysis of bipartition architecture for pipelined circuits.
APCCAS (2) 2002: 7-11 |
| 3 | EE | Yen-Jen Chang,
Feipei Lai,
Shanq-Jang Ruan:
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.
ICCD 2002: 334-339 |
| 2 | | Yen-Jen Chang,
Feipei Lai,
Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache.
IWLS 2002: 61-66 |
| 1 | EE | Shanq-Jang Ruan,
Edwin Naroska,
Yen-Jen Chang,
Feipei Lai,
Uwe Schwiegelshohn:
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits.
IEEE Trans. VLSI Syst. 10(6): 942-949 (2002) |
