2009 |
19 | EE | Daniel Menard,
Emmanuel Casseau,
Shafqat Khan,
Olivier Sentieys,
Stéphane Chevobbe,
Stéphane Guyetant,
Raphaël David:
Reconfigurable Operator Based Multimedia Embedded Processor.
ARC 2009: 39-49 |
2008 |
18 | EE | Bertrand Le Gal,
Emmanuel Casseau,
Sylvain Huet:
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis.
IEEE Trans. VLSI Syst. 16(11): 1454-1464 (2008) |
17 | EE | Bertrand Le Gal,
Emmanuel Casseau,
Caaliph Andriamisaina:
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d'applications du TDSI et gestion de cette information lors de la synthèse de haut niveau.
Technique et Science Informatiques 27(9-10): 1129-1154 (2008) |
2007 |
16 | EE | Caaliph Andriamisaina,
Emmanuel Casseau,
Philippe Coussy:
Synthesis of Multimode digital signal processing systems.
AHS 2007: 318-325 |
15 | EE | Sylvain Huet,
Sebastien LeNours,
Olivier Pasquier,
Emmanuel Casseau:
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications.
FDL 2007: 177-184 |
14 | EE | Cyrille Chavet,
Caaliph Andriamisaina,
Philippe Coussy,
Emmanuel Casseau,
Emmanuel Juin,
Pascal Urard,
Eric Martin:
A design flow dedicated to multi-mode architectures for DSP applications.
ICCAD 2007: 604-611 |
13 | EE | Philippe Coussy,
Emmanuel Casseau,
Pierre Bomel,
Adel Baganne,
Eric Martin:
Constrained algorithmic IP design for system-on-chip.
Integration 40(2): 94-105 (2007) |
2006 |
12 | EE | Sylvain Huet,
Emmanuel Casseau,
Olivier Pasquier:
A Computation Core for Communication Refinement of Digital Signal Processing Algorithms.
DSD 2006: 240-250 |
11 | EE | Sylvain Huet,
Emmanuel Casseau,
Olivier Pasquier,
Sebastien LeNours:
Hardware Communication Refinement in Digital Signal Processing.
FDL 2006: 177-185 |
10 | EE | Philippe Coussy,
Emmanuel Casseau,
Pierre Bomel,
Adel Baganne,
Eric Martin:
A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embedded Comput. Syst. 5(1): 29-53 (2006) |
9 | EE | Guillaume Savaton,
Emmanuel Casseau,
Eric Martin:
Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems.
Signal Processing 86(7): 1375-1399 (2006) |
8 | EE | Fatma Sayadi,
Emmanuel Casseau,
Mohamed Atri,
Mehrez Marzougui,
Rached Tourki,
Eric Martin:
G729 Voice Decoder Design.
VLSI Signal Processing 42(2): 173-184 (2006) |
2005 |
7 | EE | Nabil Abdelli,
Pierre Bomel,
Emmanuel Casseau,
Anne-Marie Fouilliart,
Christophe Jégo,
Philippe Kajfasz,
Bertrand Le Gal,
Nathalie Le Heno:
Hardware Virtual Components Compliant with Communication System Standards.
DSD 2005: 88-95 |
6 | EE | Sylvain Huet,
Emmanuel Casseau,
Olivier Pasquier:
Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design.
IEEE International Workshop on Rapid System Prototyping 2005: 240-243 |
5 | EE | Bertrand Le Gal,
Emmanuel Casseau,
Sylvain Huet,
Eric Martin:
Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses.
ISVLSI 2005: 268-269 |
2004 |
4 | | Emmanuel Casseau,
Bertrand Le Gal,
Christophe Jégo,
Nathalie Le Heno,
Eric Martin:
Reed-Solomon behavioral virtual component for communication systems.
ISCAS (4) 2004: 173-176 |
3 | | Emmanuel Casseau,
Christophe Jégo,
Eric Martin:
Synthèse architecturale d'applications temps réel pour technologies submicroniques.
Technique et Science Informatiques 23(1): 35-66 (2004) |
1999 |
2 | | Christophe Jégo,
Emmanuel Casseau,
Eric Martin:
Architectural Synthesis with Interconnection Cost Control.
VLSI 1999: 509-520 |
1994 |
1 | | Emmanuel Casseau,
Dominique Degrugillier:
A Linear Systolic Array for LU Decomposition.
VLSI Design 1994: 353-358 |