| 2009 |
|---|
| 22 | | Fabrizio Lombardi,
Sanjukta Bhanja,
Yehia Massoud,
R. Iris Bahar:
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
ACM 2009 |
| 21 | EE | Anita Kumari,
Javier F. Pulecio,
Sanjukta Bhanja:
Defect characterization in magnetic field coupled arrays.
ISQED 2009: 436-441 |
| 20 | EE | Karthikeyan Lingasubramanian,
Sanjukta Bhanja:
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.
VLSI Design 2009: 485-490 |
| 2008 |
|---|
| 19 | | Vijay Narayanan,
Zhiyuan Yan,
Enrico Macii,
Sanjukta Bhanja:
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008
ACM 2008 |
| 18 | EE | Sanjukta Bhanja,
Sudeep Sarkar:
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits.
IEEE Trans. VLSI Syst. 16(5): 528-541 (2008) |
| 2007 |
|---|
| 17 | EE | Karthikeyan Lingasubramanian,
Sanjukta Bhanja:
Probabilistic maximum error modeling for unreliable logic circuits.
ACM Great Lakes Symposium on VLSI 2007: 223-226 |
| 16 | EE | Saket Srivastava,
Sanjukta Bhanja:
Hierarchical Probabilistic Macromodeling for QCA Circuits.
IEEE Trans. Computers 56(2): 174-190 (2007) |
| 15 | EE | Sanjukta Bhanja,
Marco Ottavi,
Fabrizio Lombardi,
Salvatore Pontarelli:
QCA Circuits for Robust Coplanar Crossing.
J. Electronic Testing 23(2-3): 193-210 (2007) |
| 2006 |
|---|
| 14 | EE | Sanjukta Bhanja,
Marco Ottavi,
Fabrizio Lombardi,
Salvatore Pontarelli:
Novel designs for thermally robust coplanar crossing in QCA.
DATE 2006: 786-791 |
| 13 | EE | Thara Rejimon,
Sanjukta Bhanja:
Wide Limited Switch Dynamic Logic Circuit Implementations.
VLSI Design 2006: 94-99 |
| 12 | EE | Sanjukta Bhanja,
Karthikeyan Lingasubramanian,
N. Ranganathan:
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.
ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) |
| 11 | EE | Thara Rejimon,
Sanjukta Bhanja:
A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis.
IEEE Trans. VLSI Syst. 14(10): 1130-1139 (2006) |
| 2005 |
|---|
| 10 | EE | Nirmal Ramalingam,
Sanjukta Bhanja:
Causal probabilistic input dependency learning for switching model in VLSI circuits.
ACM Great Lakes Symposium on VLSI 2005: 112-115 |
| 9 | EE | Sanjukta Bhanja,
Karthikeyan Lingasubramanian,
N. Ranganathan:
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.
VLSI Design 2005: 586-591 |
| 8 | EE | Thara Rejimon,
Sanjukta Bhanja:
An Accurate Probalistic Model for Error Detection.
VLSI Design 2005: 717-722 |
| 2004 |
|---|
| 7 | EE | Shiva Shankar Ramani,
Sanjukta Bhanja:
Any-time probabilistic switching model using bayesian networks.
ISLPED 2004: 86-89 |
| 6 | EE | Sanjukta Bhanja,
N. Ranganathan:
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.
IEEE Trans. VLSI Syst. 12(12): 1360-1370 (2004) |
| 2003 |
|---|
| 5 | EE | Sanjukta Bhanja,
N. Ranganathan:
Switching activity estimation of VLSI circuits using Bayesian networks.
IEEE Trans. VLSI Syst. 11(4): 558-567 (2003) |
| 2002 |
|---|
| 4 | EE | Sanjukta Bhanja,
N. Ranganathan:
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams.
ICCD 2002: 388-390 |
| 3 | EE | Sanjukta Bhanja,
N. Ranganathan:
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks.
VLSI Design 2002: 187-192 |
| 2001 |
|---|
| 2 | EE | Sanjukta Bhanja,
N. Ranganathan:
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks.
DAC 2001: 209-214 |
| 1998 |
|---|
| 1 | | Sanjukta Bhanja,
Lynn M. Fletcher-Heath,
Lawrence O. Hall,
Dmitry B. Goldgof,
Jeffrey P. Krischer:
A Qualitative Expert System for Clinical Trial Assignment.
FLAIRS Conference 1998: 84-88 |
