| 2008 |
|---|
| 10 | EE | N. Ranganathan,
Upavan Gupta,
Venkataraman Mahalingam:
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty.
ACM Great Lakes Symposium on VLSI 2008: 171-176 |
| 9 | EE | Venkataraman Mahalingam,
Nagarajan Ranganathan:
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing.
ISVLSI 2008: 329-334 |
| 8 | EE | Venkataraman Mahalingam,
N. Ranganathan,
J. E. Harlow:
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing.
IEEE Trans. VLSI Syst. 16(8): 975-984 (2008) |
| 2007 |
|---|
| 7 | EE | Venkataraman Mahalingam,
N. Ranganathan:
Variation Aware Timing Based Placement Using Fuzzy Programming.
ISQED 2007: 327-332 |
| 2006 |
|---|
| 6 | EE | Venkataraman Mahalingam,
N. Ranganathan,
Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing.
ISLPED 2006: 174-179 |
| 5 | EE | Venkataraman Mahalingam,
N. Ranganathan:
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition.
VLSI Design 2006: 393-398 |
| 4 | EE | Venkataraman Mahalingam,
Nagarajan Ranganathan:
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.
IEEE Trans. Computers 55(12): 1523-1535 (2006) |
| 2005 |
|---|
| 3 | EE | Venkataraman Mahalingam,
N. Ranganathan:
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection.
ISVLSI 2005: 180-185 |
| 2004 |
|---|
| 2 | EE | N. Venkateswaran,
V. Barath Kumar,
R. Raghavan,
R. Srinivas,
S. Subramanian,
V. Balaji,
Venkataraman Mahalingam,
T. L. Rajaprabhu:
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.
DELTA 2004: 333-340 |
| 2003 |
|---|
| 1 | EE | N. Venkateswaran,
V. Balaji,
Venkataraman Mahalingam,
T. L. Rajaprabhu:
Analysis of Bit Transition Count for EDAC Encoded FSM.
IOLTS 2003: 166 |
