| 2009 |
|---|
| 3 | EE | Man-Lap Li,
Pradeep Ramachandran,
Ulya R. Karpuzcu,
Siva Kumar Sastry Hari,
Sarita V. Adve:
Accurate microarchitecture-level fault modeling for studying hardware faults.
HPCA 2009: 105-116 |
| 2008 |
|---|
| 2 | EE | Siva Kumar Sastry Hari,
Vishnu Vardhan Reddy Konda,
V. Kamakoti,
Vivekananda M. Vedula,
K. S. Maneperambil:
Automatic Constraint Based Test Generation for Behavioral HDL Models.
IEEE Trans. VLSI Syst. 16(4): 408-421 (2008) |
| 2007 |
|---|
| 1 | EE | K. Najeeb,
Vishnu Vardhan Reddy Konda,
Siva Kumar Sastry Hari,
V. Kamakoti,
Vivekananda M. Vedula:
Power Virus Generation Using Behavioral Models of Circuits.
VTS 2007: 35-42 |
