2008 | ||
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19 | EE | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. IEEE Trans. VLSI Syst. 16(7): 830-836 (2008) |
2007 | ||
18 | EE | Tim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross: A hardware architecture for surface splatting. ACM Trans. Graph. 26(3): 90 (2007) |
2006 | ||
17 | EE | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159 |
16 | EE | Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. DAC 2006: 558-561 |
15 | EE | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Two-phase resonant clocking for ultra-low-power hearing aid applications. DATE 2006: 73-78 |
14 | EE | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: 42% power savings through glitch-reducing clocking strategy in a hearing aid application. ISCAS 2006 |
13 | EE | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electr. Notes Theor. Comput. Sci. 146(2): 133-149 (2006) |
2005 | ||
12 | EE | Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. PATMOS 2005: 446-455 |
2004 | ||
11 | EE | Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin: A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 |
2003 | ||
10 | EE | Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner: Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2003: 141-150 |
9 | EE | Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner: Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116 |
2002 | ||
8 | EE | Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189 |
7 | EE | A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner: 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES 2002: 144-158 |
2001 | ||
6 | EE | Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21(2): 69-80 (2001) |
1999 | ||
5 | Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann: Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC 1999: 414-420 | |
1996 | ||
4 | Robert Rogenmoser, Hubert Kaeslin, Tobias Blickle: Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. PPSN 1996: 849-858 | |
1993 | ||
3 | H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner: VINCI: Secure Test of a VLSI High-Speed Encryption System. ITC 1993: 782-790 | |
1991 | ||
2 | H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai: VLSI Implementation of a New Block Cipher. ICCD 1991: 510-513 | |
1988 | ||
1 | Hubert Kaeslin: Application of Graph Theory to Topology Generation for Logic Gates. WG 1988: 304-316 |