| 2008 |
|---|
| 14 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
Automatic verification of safety and liveness for pipelined machines using WEB refinement.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 13 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification.
IEEE Trans. VLSI Syst. 16(4): 353-364 (2008) |
| 2007 |
|---|
| 12 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan,
Daron Vroon:
BAT: The Bit-Level Analysis Tool.
CAV 2007: 303-306 |
| 2006 |
|---|
| 11 | EE | Roma Kane,
Panagiotis Manolios,
Sudarshan K. Srinivasan:
Monolithic verification of deep pipelines with collapsed flushing.
DATE 2006: 1234-1239 |
| 10 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan,
Daron Vroon:
Automatic memory reductions for RTL model verification.
ICCAD 2006: 786-793 |
| 9 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.
J. Autom. Reasoning 37(1-2): 93-116 (2006) |
| 2005 |
|---|
| 8 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.
CHARME 2005: 363-366 |
| 7 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
Refinement Maps for Efficient Verification of Processor Models.
DATE 2005: 1304-1309 |
| 6 | | Panagiotis Manolios,
Sudarshan K. Srinivasan:
Verification of executable pipelined machines with bit-level interfaces.
ICCAD 2005: 855-862 |
| 5 | | Panagiotis Manolios,
Sudarshan K. Srinivasan:
A complete compositional reasoning framework for the efficient verification of pipelined machines.
ICCAD 2005: 863-870 |
| 4 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines.
MEMOCODE 2005: 188-197 |
| 2004 |
|---|
| 3 | EE | Panagiotis Manolios,
Sudarshan K. Srinivasan:
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements.
DATE 2004: 168-175 |
| 2003 |
|---|
| 2 | EE | Sudarshan K. Srinivasan,
Miroslav N. Velev:
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions.
MEMOCODE 2003: 65-74 |
| 1 | EE | Jun-Cheol Park,
Vincent John Mooney III,
Sudarshan K. Srinivasan:
Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems.
Microelectronics Journal 34(11): 1019-1024 (2003) |
