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Sudarshan K. Srinivasan

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2008
14EEPanagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
13EEPanagiotis Manolios, Sudarshan K. Srinivasan: A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. IEEE Trans. VLSI Syst. 16(4): 353-364 (2008)
2007
12EEPanagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: BAT: The Bit-Level Analysis Tool. CAV 2007: 303-306
2006
11EERoma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan: Monolithic verification of deep pipelines with collapsed flushing. DATE 2006: 1234-1239
10EEPanagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: Automatic memory reductions for RTL model verification. ICCAD 2006: 786-793
9EEPanagiotis Manolios, Sudarshan K. Srinivasan: A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. J. Autom. Reasoning 37(1-2): 93-116 (2006)
2005
8EEPanagiotis Manolios, Sudarshan K. Srinivasan: A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME 2005: 363-366
7EEPanagiotis Manolios, Sudarshan K. Srinivasan: Refinement Maps for Efficient Verification of Processor Models. DATE 2005: 1304-1309
6 Panagiotis Manolios, Sudarshan K. Srinivasan: Verification of executable pipelined machines with bit-level interfaces. ICCAD 2005: 855-862
5 Panagiotis Manolios, Sudarshan K. Srinivasan: A complete compositional reasoning framework for the efficient verification of pipelined machines. ICCAD 2005: 863-870
4EEPanagiotis Manolios, Sudarshan K. Srinivasan: A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. MEMOCODE 2005: 188-197
2004
3EEPanagiotis Manolios, Sudarshan K. Srinivasan: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. DATE 2004: 168-175
2003
2EESudarshan K. Srinivasan, Miroslav N. Velev: Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions. MEMOCODE 2003: 65-74
1EEJun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan: Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems. Microelectronics Journal 34(11): 1019-1024 (2003)

Coauthor Index

1Roma Kane [11]
2Panagiotis Manolios [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
3Vincent John Mooney III (Vincent John Mooney) [1]
4Jun-Cheol Park [1]
5Miroslav N. Velev [2]
6Daron Vroon [10] [12]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)