Ashoka Visweswara Sathanur

2008
14	EE	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI 2008: 177-182
13	EE	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE 2008: 379-384
12	EE	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764
11	EE	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. ISLPED 2008: 51-56
10	EE	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. PATMOS 2008: 42-51
9	EE	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. VLSI Syst. 16(6): 639-649 (2008)
8	EE	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integration 41(1): 2-8 (2008)
2007
7	EE	Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
6	EE	Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE 2007: 1544-1549
5	EE	Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino: Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. ISCAS 2007: 1061-1064
4	EE	Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Timing-driven row-based power gating. ISLPED 2007: 104-109
2006
3	EE	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS 2006
2	EE	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED 2006: 162-167
1	EE	Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino: Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS 2006: 214-224

Coauthor Index

1	Luca Benini	[2] [4] [6] [7] [9] [10] [11] [12] [13] [14]
2	Andrea Calimera	[6] [7] [12]
3	Ashutosh Chakraborty	[1] [2] [3] [8] [9]
4	Karthik Duraisami	[1] [2] [3] [5] [8] [9]
5	Alberto Macii	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
6	Enrico Macii	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
7	Massimo Poncino	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
8	Antonio Pullini	[4] [7] [12] [13] [14]
9	Prassanna Sithambaram	[1] [2] [3] [5] [8] [9]