Sara Blanc

List of publications from the DBLP Bibliography Server - FAQ

2008

4 EE Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil: Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. IEEE Trans. VLSI Syst. 16(6): 693-706 (2008)

2004

3 EE Sara Blanc, Joaquin Gracia, Pedro J. Gil: Experiences during the Experimental Validation of the Time-Triggered Architecture. DATE 2004: 256-261

2003

2 EE Sara Blanc, Pedro J. Gil: Improving the Multiple Errors Detection Coverage in Distributed Embedded Systems. SRDS 2003: 303-

2002

1 EE Sara Blanc, Joaquin Gracia, Pedro J. Gil: A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. DFT 2002: 254-262

2008
4	EE	Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil: Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. IEEE Trans. VLSI Syst. 16(6): 693-706 (2008)
2004
3	EE	Sara Blanc, Joaquin Gracia, Pedro J. Gil: Experiences during the Experimental Validation of the Time-Triggered Architecture. DATE 2004: 256-261
2003
2	EE	Sara Blanc, Pedro J. Gil: Improving the Multiple Errors Detection Coverage in Distributed Embedded Systems. SRDS 2003: 303-
2002
1	EE	Sara Blanc, Joaquin Gracia, Pedro J. Gil: A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. DFT 2002: 254-262

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