| 2008 |
|---|
| 109 | EE | Hani Saleh,
Earl E. Swartzlander Jr.:
A floating-point fused dot-product unit.
ICCD 2008: 427-431 |
| 108 | EE | Xin Yang,
Jun Mu,
Sakir Sezer,
John V. McCanny,
Earl E. Swartzlander Jr.:
High performance IP lookup circuit using DDR SDRAM.
SoCC 2008: 371-374 |
| 107 | EE | Earl E. Swartzlander Jr.:
Fixed-Point Computer Arithmetic.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 106 | EE | Eric Quinnell,
Earl E. Swartzlander Jr.:
Floating-Point Computer Arithmetic.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 105 | EE | Eric Quinnell,
Earl E. Swartzlander Jr.,
Carl Lemonds:
Bridge Floating-Point Fused Multiply-Add Design.
IEEE Trans. VLSI Syst. 16(12): 1727-1731 (2008) |
| 104 | EE | Youngmoon Choi,
Earl E. Swartzlander Jr.:
Speculative Carry Generation With Prefix Adder.
IEEE Trans. VLSI Syst. 16(3): 321-326 (2008) |
| 103 | EE | Robert T. Grisamore,
Earl E. Swartzlander Jr.:
Negative Save Sign Extension for Multi-term Adders and Multipliers.
Signal Processing Systems 52(1): 1-11 (2008) |
| 102 | EE | Earl E. Swartzlander Jr.:
Systolic FFT Processors: A Personal Perspective.
Signal Processing Systems 53(1-2): 3-14 (2008) |
| 2007 |
|---|
| 101 | EE | Hani Saleh,
Bassam Jamil Mohd,
Adnan Aziz,
Earl E. Swartzlander Jr.:
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine.
ICCD 2007: 7-12 |
| 100 | EE | Heumpil Cho,
Earl E. Swartzlander Jr.:
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata.
IEEE Symposium on Computer Arithmetic 2007: 7-15 |
| 99 | EE | Bassam Jamil Mohd,
Adnan Aziz,
Earl E. Swartzlander Jr.:
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture.
VLSI-SoC 2007: 194-199 |
| 98 | EE | Earl E. Swartzlander Jr.:
The Negative Two's Complement Number System.
VLSI Signal Processing 49(1): 177-183 (2007) |
| 2006 |
|---|
| 97 | EE | Tung N. Pham,
Earl E. Swartzlander Jr.:
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology.
ASAP 2006: 105-108 |
| 96 | EE | Earl E. Swartzlander Jr.:
Systolic FFT Processors: Past, Present and Future.
ASAP 2006: 153-158 |
| 2005 |
|---|
| 95 | EE | Moboluwaji O. Sanu,
Earl E. Swartzlander Jr.:
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields.
ASAP 2005: 134-139 |
| 94 | EE | Youngmoon Choi,
Earl E. Swartzlander Jr.:
Parallel Prefix Adder Design with Matrix Representation.
IEEE Symposium on Computer Arithmetic 2005: 90-98 |
| 93 | EE | Earl E. Swartzlander Jr.:
Three Dimensional System on Chip Technology, invited.
IWSOC 2005: 465-470 |
| 2004 |
|---|
| 92 | EE | Moboluwaji O. Sanu,
Earl E. Swartzlander Jr.,
Craig M. Chase:
Parallel Montgomery Multipliers.
ASAP 2004: 63-72 |
| 91 | EE | Earl E. Swartzlander Jr.:
A Review of Large Parallel Counter Designs.
ISVLSI 2004: 89-98 |
| 2003 |
|---|
| 90 | EE | Ayman M. El-Khashab,
Earl E. Swartzlander Jr.:
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform.
ASAP 2003: 378-388 |
| 89 | EE | Whitney J. Townsend,
Jacob A. Abraham,
Earl E. Swartzlander Jr.:
Quadruple Time Redundancy Adders.
DFT 2003: 250-256 |
| 88 | EE | J. Yoo,
E. Lee,
Earl E. Swartzlander Jr.:
A self-testing method for the pipelined A/D converter.
ISCAS (1) 2003: 109-112 |
| 87 | EE | Mohammad Ibrahim,
Earl E. Swartzlander Jr.:
Guest Editorial.
VLSI Signal Processing 33(1-2): 5 (2003) |
| 2002 |
|---|
| 86 | EE | Chang Yong Kang,
Earl E. Swartzlander Jr.:
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis.
ASAP 2002: 111-119 |
| 85 | EE | Steven M. Currie,
Paul R. Schumacher,
Barry K. Gilbert,
Earl E. Swartzlander Jr.,
Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS.
ASAP 2002: 335-343 |
| 84 | EE | Ohsang Kwon,
Kevin J. Nowka,
Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells.
VLSI Signal Processing 31(2): 77-89 (2002) |
| 2001 |
|---|
| 83 | EE | Ohsang Kwon,
Earl E. Swartzlander Jr.,
Kevin J. Nowka:
A fast hybrid carry-lookahead/carry-select adder design.
ACM Great Lakes Symposium on VLSI 2001: 149-152 |
| 82 | EE | Tat Ngai,
Earl E. Swartzlander Jr.,
Chen He:
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic.
DFT 2001: 78-83 |
| 81 | EE | K'Andrea C. Bickerstaff,
Earl E. Swartzlander Jr.,
Michael J. Schulte:
Analysis of Column Compression Multipliers.
IEEE Symposium on Computer Arithmetic 2001: 33-39 |
| 80 | EE | Sungwook Yu,
Earl E. Swartzlander Jr.:
DCT Implementation with Distributed Arithmetic.
IEEE Trans. Computers 50(9): 985-991 (2001) |
| 2000 |
|---|
| 79 | EE | Ohsang Kwon,
Earl E. Swartzlander Jr.,
Kevin J. Nowka:
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors.
ASAP 2000: 235- |
| 78 | EE | Jae-Hyuck Kwak,
Earl E. Swartzlander Jr.,
Vincenzo Piuri:
Fault-Tolerant High-Performance Cordic Processors.
DFT 2000: 164-172 |
| 77 | EE | Hyesook Lim,
Vincenzo Piuri,
Earl E. Swartzlander Jr.:
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms.
IEEE Trans. Computers 49(12): 1297-1309 (2000) |
| 76 | EE | Michael J. Schulte,
Earl E. Swartzlander Jr.:
A Family of Variable-Precision Interval Arithmetic Processors.
IEEE Trans. Computers 49(5): 387-397 (2000) |
| 75 | EE | W. Lynn Gallagher,
Earl E. Swartzlander Jr.:
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR.
IEEE Trans. Computers 49(6): 588-595 (2000) |
| 74 | EE | Jae-Hyuck Kwak,
Jae Hun Choi,
Earl E. Swartzlander Jr.:
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method.
VLSI Signal Processing 25(2): 167-177 (2000) |
| 1999 |
|---|
| 73 | EE | W. Lynn Gallagher,
Earl E. Swartzlander Jr.:
Power Consumption in Fast Dividers Using Time Shared TMR.
DFT 1999: 256-264 |
| 72 | EE | Vincenzo Piuri,
Earl E. Swartzlander Jr.:
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors.
DFT 1999: 265-273 |
| 71 | EE | Jae Hun Choi,
Jae-Hyuck Kwak,
Earl E. Swartzlander Jr.:
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection.
ICCD 1999: 68-72 |
| 70 | EE | Gwangwoo Choe,
Earl E. Swartzlander Jr.:
Bipolar merged arithmetic for wavelet architectures.
ISCAS (3) 1999: 462-465 |
| 69 | | Francescomaria Marino,
Earl E. Swartzlander Jr.:
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication.
IEEE Trans. Computers 48(9): 951-961 (1999) |
| 1998 |
|---|
| 68 | EE | W. Lynn Gallagher,
Earl E. Swartzlander Jr.:
Error-Correcting Goldschmidt Dividers Using Time Shared TMR.
DFT 1998: 224-232 |
| 67 | EE | Gwangwoo Choe,
Earl E. Swartzlander Jr.:
Merged Arithmetic for Computing Wavelet Transforms.
Great Lakes Symposium on VLSI 1998: 196-201 |
| 66 | | Earl E. Swartzlander Jr.:
Calculators.
IEEE Annals of the History of Computing 20(1): 67-76 (1998) |
| 65 | | Earl E. Swartzlander Jr.:
Calculators.
IEEE Annals of the History of Computing 20(3): 72-73 (1998) |
| 64 | EE | Earl E. Swartzlander Jr.:
VLSI, MCM, and WSI: A Design Comparison.
IEEE Design & Test of Computers 15(3): 28-34 (1998) |
| 63 | EE | Mary Jane Irwin,
S. Y. Kung,
Earl E. Swartzlander Jr.:
Editorial Message.
VLSI Signal Processing 18(1): 7-8 (1998) |
| 1997 |
|---|
| 62 | EE | Hercule Kwan,
Edward J. Powers,
Earl E. Swartzlander Jr.:
Realization of a nonlinear digital filter on a DSP array processor.
ASAP 1997: 24-33 |
| 61 | EE | W. Lynn Gallagher,
Earl E. Swartzlander Jr.:
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR.
DFT 1997: 243-251 |
| 60 | EE | Thomas K. Callaway,
Earl E. Swartzlander Jr.:
Power-Delay Characteristics of CMOS Multipliers.
IEEE Symposium on Computer Arithmetic 1997: 26- |
| 59 | EE | Edwin de Angel,
Earl E. Swartzlander Jr.:
Survey of low power techniques for ROMs.
ISLPED 1997: 7-11 |
| 58 | | Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic.
The Computer Science and Engineering Handbook 1997: 462-481 |
| 57 | | Earl E. Swartzlander Jr.:
Calculators.
IEEE Annals of the History of Computing 19(1): 74-75 (1997) |
| 56 | | Shaoyun Wang,
Vincenzo Piuri,
Earl E. Swartzlander Jr.:
Hybrid CORDIC Algorithms.
IEEE Trans. Computers 46(11): 1202-1207 (1997) |
| 1996 |
|---|
| 55 | EE | Hyesook Lim,
Changhoon Yim,
Earl E. Swartzlander Jr.:
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT.
ASAP 1996: 35- |
| 54 | EE | Earl E. Swartzlander Jr.:
Calculators.
IEEE Annals of the History of Computing 18(3): 70-71 (1996) |
| 53 | EE | Earl E. Swartzlander Jr.:
Calculators.
IEEE Annals of the History of Computing 18(4): 62-64 (1996) |
| 52 | EE | Hercule Kwan,
Robert Leonard Nelson Jr.,
Earl E. Swartzlander Jr.:
A new design for a lookahead carry generator.
VLSI Signal Processing 14(3): 295-302 (1996) |
| 1995 |
|---|
| 51 | EE | Michael J. Schulte,
Earl E. Swartzlander Jr.:
A Processor for Staggered Interval Arithmetic.
ASAP 1995: 104-112 |
| 50 | EE | Yuang-Ming Hsu,
Earl E. Swartzlander Jr.,
Vincenzo Piuri:
Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks.
ASAP 1995: 54-65 |
| 49 | EE | Hyesook Lim,
Earl E. Swartzlander Jr.:
An efficient systolic array for the discrete cosine transform based on prime-factor decomposition .
ICCD 1995: 644-649 |
| 48 | EE | Michael J. Schulte,
Earl E. Swartzlander Jr.:
A coprocessor for accurate and reliable numerical computations.
ICCD 1995: 686- |
| 47 | EE | Hercule Kwan,
Robert Leonard Nelson Jr.,
Earl E. Swartzlander Jr.:
Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead.
IEEE Symposium on Computer Arithmetic 1995: 115- |
| 46 | EE | Michael J. Schulte,
Earl E. Swartzlander Jr.:
Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor.
IEEE Symposium on Computer Arithmetic 1995: 222-229 |
| 45 | | Shaoyun Wang,
Earl E. Swartzlander Jr.:
Merged CORDIC Algorithm.
ISCAS 1995: 1988-1991 |
| 44 | | Yuang-Ming Hsu,
Vincenzo Piuri,
Earl E. Swartzlander Jr.:
Fault-Tolerant Neural Architectures: The Use of Rotated Operands.
ISCAS 1995: 2201-2204 |
| 43 | | Yuang-Ming Hsu,
Vincenzo Piuri,
Earl E. Swartzlander Jr.:
Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks.
ISCAS 1995: 977-980 |
| 42 | EE | K'Andrea C. Bickerstaff,
Michael J. Schulte,
Earl E. Swartzlander Jr.:
Parallel reduced area multipliers.
VLSI Signal Processing 9(3): 181-191 (1995) |
| 1994 |
|---|
| 41 | | Yuang-Ming Hsu,
Earl E. Swartzlander Jr.:
Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers.
DFT 1994: 159-167 |
| 40 | | Edwin de Angel,
Earl E. Swartzlander Jr.,
Jacob A. Abraham:
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic.
ICCD 1994: 302-305 |
| 39 | | José Duato,
C. T. Howard Ho,
Ferng-Ching Lin,
Lionel M. Ni,
Earl E. Swartzlander Jr.:
Is It Possible to Fairly Compare Interconnection Networks?.
ICPADS 1994: 16-19 |
| 38 | | Thomas L. Casavant,
Chi-Yuan Chin,
Wen-Tsuen Chen,
Kang G. Shin,
Earl E. Swartzlander Jr.,
Joseph E. Urban:
What Types of Research Papers Should We Be Writing?
ICPADS 1994: 22-23 |
| 37 | | Yuang-Ming Hsu,
Earl E. Swartzlander Jr.:
Sorting Networks with Built-In Error Correction.
ICPADS 1994: 379-385 |
| 36 | | Earl E. Swartzlander Jr.:
Heterogeneous Parallel Computing.
ICPADS 1994: 8-9 |
| 35 | | Mohammad S. Khan,
Earl E. Swartzlander Jr.:
A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors.
ISCAS 1994: 97-100 |
| 34 | | Michael J. Schulte,
Earl E. Swartzlander Jr.:
Hardware Designs for Exactly Rounded Elemantary Functions.
IEEE Trans. Computers 43(8): 964-973 (1994) |
| 33 | EE | Thomas A. Ziaja,
Earl E. Swartzlander Jr.:
Boundary scan in board manufacturing.
J. Electronic Testing 5(2-3): 263-268 (1994) |
| 32 | EE | Robert F. Jones,
Earl E. Swartzlander Jr.:
Parallel counter implementation.
VLSI Signal Processing 7(3): 223-232 (1994) |
| 31 | EE | Ben C. Drerup,
Earl E. Swartzlander Jr.:
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation.
VLSI Signal Processing 7(3): 249-257 (1994) |
| 30 | EE | Earl E. Swartzlander Jr.:
Editorial.
VLSI Signal Processing 8(1): 5 (1994) |
| 1993 |
|---|
| 29 | | Earl E. Swartzlander Jr.,
Mary Jane Irwin,
Graham A. Jullien:
11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings.
IEEE Computer Society/ 1993 |
| 28 | | Yuang-Ming Hsu,
Earl E. Swartzlander Jr.:
VLSI Concurrent Error Correcting Adders and Multipliers.
DFT 1993: 287-294 |
| 27 | | Rathish Jayabharathi,
Thomas Thomas,
Earl E. Swartzlander Jr.:
A Comparative Evaluation of Adders Based on Performance and Testability.
ICCD 1993: 314-317 |
| 26 | EE | Michael J. Schulte,
Earl E. Swartzlander Jr.:
Exact rounding of certain elementary functions.
IEEE Symposium on Computer Arithmetic 1993: 138-145 |
| 25 | EE | Thomas K. Callaway,
Earl E. Swartzlander Jr.:
Estimating the power consumption of CMOS adders.
IEEE Symposium on Computer Arithmetic 1993: 210-216 |
| 24 | | Ishaq H. Unwala,
Earl E. Swartzlander Jr.:
Superpipelined Adder Designs.
ISCAS 1993: 1841-1844 |
| 23 | EE | Philip E. Madrid,
Brian Millar,
Earl E. Swartzlander Jr.:
Modified Booth algorithm for high radix fixed-point multiplication.
IEEE Trans. VLSI Syst. 1(2): 164-167 (1993) |
| 1992 |
|---|
| 22 | | Vijay K. Jain,
Gibert E. Perez,
Earl E. Swartzlander Jr.:
Arithmetic Error Analysis of a new Reciprocal Cell.
ICCD 1992: 106-109 |
| 21 | | Philip E. Madrid,
Brian Millar,
Earl E. Swartzlander Jr.:
Modified Booth Algorihtm for High Radix Multiplication.
ICCD 1992: 118-121 |
| 20 | | Thomas K. Callaway,
Earl E. Swartzlander Jr.:
Implementation of Parallel Processors with Wafer Scale Integration.
IPPS 1992: 268-274 |
| 19 | | W. Kent Fuchs,
Earl E. Swartzlander Jr.:
Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction.
IEEE Computer 25(4): 6-8 (1992) |
| 18 | | Thomas Lynch,
Earl E. Swartzlander Jr.:
A Spanning Tree Carry Lookahead Adder.
IEEE Trans. Computers 41(8): 931-939 (1992) |
| 17 | EE | Earl E. Swartzlander Jr.,
Vijay K. Jain,
Hiroomi Hikawa:
A radix-8 wafer scale FFT processor.
VLSI Signal Processing 4(2-3): 165-176 (1992) |
| 1990 |
|---|
| 16 | EE | Earl E. Swartzlander Jr.:
Editorial.
VLSI Signal Processing 2(1): 5 (1990) |
| 15 | EE | Earl E. Swartzlander Jr.:
Generic signal processor implementation with VHSIC.
VLSI Signal Processing 2(2): 111-116 (1990) |
| 1989 |
|---|
| 14 | EE | Earl E. Swartzlander Jr.:
Editorial.
VLSI Signal Processing 1(1): 5 (1989) |
| 13 | EE | Earl E. Swartzlander Jr.:
Editorial.
VLSI Signal Processing 1(2): 91 (1989) |
| 12 | EE | Earl E. Swartzlander Jr.:
Editorial.
VLSI Signal Processing 1(3): 167 (1989) |
| 1985 |
|---|
| 11 | | Earl E. Swartzlander Jr.,
John A. Eldon,
De D. Hsu:
VLSI Testing: A Decade of Experience.
COMPCON 1985: 392-396 |
| 10 | | Stephen F. Lundstrom,
Earl E. Swartzlander Jr.:
Foreword: Advances in Distributed Computing Systems.
IEEE Trans. Software Eng. 11(10): 1092-1096 (1985) |
| 1983 |
|---|
| 9 | | Earl E. Swartzlander Jr.,
D. V. Satish Chandra,
H. Troy Nagle Jr.,
Scott A. Starks:
Sign/Logarithm Arithmetic for FFT Implementation.
IEEE Trans. Computers 32(6): 526-534 (1983) |
| 1982 |
|---|
| 8 | | Earl E. Swartzlander Jr.,
Barry K. Gilbert:
Supersystems: Technology and Architecture.
IEEE Trans. Computers 31(5): 399-409 (1982) |
| 1980 |
|---|
| 7 | | Earl E. Swartzlander Jr.:
Merged Arithmetic.
IEEE Trans. Computers 29(10): 946-950 (1980) |
| 6 | | Earl E. Swartzlander Jr.,
Barry K. Gilbert:
Arithmetic for Ultra-High-Speed Tomography.
IEEE Trans. Computers 29(5): 341-353 (1980) |
| 1979 |
|---|
| 5 | | Earl E. Swartzlander Jr.:
Microprogrammed Control for Specialized Processors.
IEEE Trans. Computers 28(12): 930-934 (1979) |
| 4 | | Earl E. Swartzlander Jr.,
Douglas J. Heath:
A Routing Algorithm for Signal Processing Networks.
IEEE Trans. Computers 28(8): 567-572 (1979) |
| 3 | | Earl E. Swartzlander Jr.:
Comment on ``The Focus Number System''.
IEEE Trans. Computers 28(9): 693 (1979) |
| 1978 |
|---|
| 2 | | Earl E. Swartzlander Jr.,
Barry K. Gilbert,
Irving S. Reed:
Inner Product Computers.
IEEE Trans. Computers 27(1): 21-31 (1978) |
| 1975 |
|---|
| 1 | | Earl E. Swartzlander Jr.,
Aristides G. Alexopoulos:
The Sign/Logarithm Number System.
IEEE Trans. Computers 24(12): 1238-1242 (1975) |
