| 2008 |
|---|
| 9 | EE | Sheng-Chih Lin,
Kaustav Banerjee:
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies.
IEEE Trans. VLSI Syst. 16(11): 1488-1498 (2008) |
| 2007 |
|---|
| 8 | EE | Shashidhar Mysore,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Kaustav Banerjee,
Timothy Sherwood:
3D Integration for Introspection.
IEEE Micro 27(1): 77-83 (2007) |
| 2006 |
|---|
| 7 | EE | Kaustav Banerjee,
Sheng-Chih Lin,
Navin Srivastava:
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.
ASP-DAC 2006: 223-230 |
| 6 | EE | Shashidhar Mysore,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Kaustav Banerjee,
Timothy Sherwood:
Introspective 3D chips.
ASPLOS 2006: 264-273 |
| 5 | EE | Gian Luca Loi,
Banit Agrawal,
Navin Srivastava,
Sheng-Chih Lin,
Timothy Sherwood,
Kaustav Banerjee:
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy.
DAC 2006: 991-996 |
| 4 | EE | Sheng-Chih Lin,
Kaustav Banerjee:
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.
ICCAD 2006: 568-574 |
| 2005 |
|---|
| 3 | EE | Sheng-Chih Lin,
Navin Srivastava,
Kaustav Banerjee:
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.
ICCD 2005: 411-416 |
| 2004 |
|---|
| 2 | EE | Anirban Basu,
Sheng-Chih Lin,
Vineet Wason,
Amit Mehrotra,
Kaustav Banerjee:
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era.
DAC 2004: 884-887 |
| 1 | EE | Anirban Basu,
Sheng-Chih Lin,
Christoph Wasshuber,
Adrian M. Ionescu,
Kaustav Banerjee:
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array.
ISQED 2004: 259-264 |
