Wayne P. Burleson

Wayne Burleson

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo
Home Page

75EEBasab Datta, Wayne P. Burleson: Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensors. ACM Great Lakes Symposium on VLSI 2009: 145-148
74EEBasab Datta, Wayne Burleson: On temperature planarization effect of copper dummy fills in deep nanometer technology. ISQED 2009: 494-499
73EEBasab Datta, Wayne Burleson: Temperature effects on energy optimization in sub-threshold circuit design. ISQED 2009: 680-685
72EEBasab Datta, Wayne Burleson: Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. ACM Great Lakes Symposium on VLSI 2008: 41-46
71EEVenkatesh Arunachalam, Wayne Burleson: Low-power clock distribution in a multilayer core 3d microprocessor. ACM Great Lakes Symposium on VLSI 2008: 429-434
70EELang Lin, Wayne Burleson: Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems. ISCAS 2008: 252-255
69EEBasab Datta, Wayne P. Burleson: Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. SoCC 2008: 147-150
68EEGuy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin: Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective. IEEE Trans. VLSI Syst. 16(2): 144-155 (2008)
67 Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne Burleson: High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123
66EESheng Xu, Ibis Benito, Wayne P. Burleson: Thermal Impacts on NoC Interconnects. NOCS 2007: 220
65 Romain Vaslin, Guy Gogniat, Eduardo Wanderley Netto, Russell Tessier, Wayne P. Burleson: Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153
64EEBasab Datta, Wayne P. Burleson: Low power on-chip thermal sensors based on wires. VLSI-SoC 2007: 258-263
63EEAtul Maheshwari, Wayne Burleson: Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. IEEE Trans. VLSI Syst. 15(11): 1239-1244 (2007)
62EEGuy Gogniat, Tilman Wolf, Wayne Burleson: Reconfigurable Security Support for Embedded Systems. HICSS 2006
61EELilian Bossuet, Guy Gogniat, Wayne Burleson: Dynamically configurable security for SRAM FPGA bitstreams. IJES 2(1/2): 73-85 (2006)
60EEVishak Venkatraman, Wayne Burleson: Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. ISQED 2005: 522-527
59EEAiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson: Sensing Design Issues in Deep Submicron CMOS SRAMs. ISVLSI 2005: 42-45
58EEJinwook Jang, Sheng Xu, Wayne Burleson: Jitter in Deep Sub-Micron Interconnect. ISVLSI 2005: 84-89
57EEWayne Burleson, Sheng Xu: Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats. MSE 2005: 3-4
56EEGuy Gogniat, Wayne Burleson, Lilian Bossuet: Configurable Computing for High-Security/High-Performance Ambient Systems. SAMOS 2005: 72-81
55EEVishak Venkatraman, Wayne Burleson: Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. VLSI Design 2005: 362-367
54EEMatthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. IEEE Trans. Computers 54(12): 1532-1546 (2005)
53EERussell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson: An energy-aware active smart card. IEEE Trans. VLSI Syst. 13(10): 1190-1199 (2005)
52EERussell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson: A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Trans. VLSI Syst. 13(4): 484-488 (2005)
51EEJeongseon Euh, Jeevan Chittamuru, Wayne Burleson: Power-Aware 3D Computer Graphics Rendering. VLSI Signal Processing 39(1-2): 15-33 (2005)
50EEVishak Venkatraman, Atul Maheshwari, Wayne Burleson: Mitigating static power in current-sensed interconnects. ACM Great Lakes Symposium on VLSI 2004: 224-229
49EEMatthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. DATE 2004: 410-415
48EELilian Bossuet, Guy Gogniat, Wayne Burleson: Dynamically Configurable Security for SRAM FPGA Bitstreams. IPDPS 2004
47EEVishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson: NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. SLIP 2004: 69-75
46 Atul Maheshwari, Wayne Burleson, Russell Tessier: Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. VLSI Syst. 12(3): 299-311 (2004)
45EEPrashant Jain, Andrew Laffely, Wayne Burleson, Russell Tessier, Dennis Goeckel: Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. VLSI Signal Processing 36(1): 27-40 (2004)
44EEAtul Maheshwari, Wayne Burleson: Repeater and current-sensing hybrid circuits for on-chip interconnects. ACM Great Lakes Symposium on VLSI 2003: 269-272
43EEAiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier: A hybrid adiabatic content addressable memory for ultra low-power applications. ACM Great Lakes Symposium on VLSI 2003: 72-75
42EEAtul Maheshwari, Israel Koren, Wayne Burleson: Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. DFT 2003: 597-
41 Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson: Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108
40EELilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe: Targeting Tiled Architectures in Design Exploration. IPDPS 2003: 172
39EESrividya Srinivasaraghavan, Wayne Burleson: Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. ISVLSI 2003: 55-61
38EEAndrew Laffely, Wayne Burleson: Using System On-A-Chip As A Vehicle For VLSI Design Education. MSE 2003: 148-149
37EESriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson: A dynamically reconfigurable adaptive viterbi decoder. FPGA 2002: 227-236
36EEAtul Maheshwari, Wayne Burleson, Russell Tessier: Trading off Reliability and Power-Consumption in Ultra-low Power Systems. ISQED 2002: 361-366
35EEJeongseon Euh, Jeevan Chittamuru, Wayne Burleson: A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics. PACS 2002: 99-109
34EEAnkireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson: Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 50-62 (2002)
33EEAnkireddy Nalamalpu, Wayne Burleson: Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. ISPD 2001: 204-211
32EEWayne Burleson, Prashant Jain, Subramanian Venkatraman: Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT. Workshop on Digital and Computational Video 2001: 4-12
31EEWayne Burleson, Naresh R. Shanbhag: Guest Editorial: Reconfigurable Signal Processing Systems. VLSI Signal Processing 28(1-2): 5-6 (2001)
30EERussell Tessier, Wayne Burleson: Reconfigurable Computing for Digital Signal Processing: A Survey. VLSI Signal Processing 28(1-2): 7-27 (2001)
29EEAndrés D. García, Jean-Luc Danger, Wayne P. Burleson: Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption. FPGA 2000: 220
28 J. Peden, Wayne Burleson, C. Leonardo: The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning. IEEE International Conference on Multimedia and Expo (II) 2000: 593-596
27EEJeongseon Euh, Wayne Burleson: Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. PACS 2000: 51-64
26EEElias S. Manolakos, Wayne Burleson: Guest Editor's Introduction. VLSI Signal Processing 24(1): 5-6 (2000)
25EES. R. Park, Wayne Burleson: Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures. FPGA 1999: 81-89
24 Andrés D. García, Wayne P. Burleson, Jean-Luc Danger: Power Modelling in Field Programmable Gate Arrays (FPGA). FPL 1999: 396-404
23EEWayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems: The spring scheduling coprocessor: a scheduling accelerator. IEEE Trans. VLSI Syst. 7(1): 38-47 (1999)
22EEWayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu: Wave-pipelining: a tutorial and research survey. IEEE Trans. VLSI Syst. 6(3): 464-474 (1998)
21EEBongjin Jung, Wayne P. Burleson: Efficient VLSI for Lempel-Ziv compression in wireless data communication networks. IEEE Trans. VLSI Syst. 6(3): 475-483 (1998)
20EEBongjin Jung, Wayne P. Burleson: Vlsi Array Architectures for Pyramid Vector Quantization. VLSI Signal Processing 18(2): 141-154 (1998)
19EEWayne P. Burleson, Konstantinos Konstantinides: Guest Editors' Introduction. VLSI Signal Processing 18(2): 87-88 (1998)
18EEBongjin Jung, Wayne P. Burleson: Performance optimization of wireless local area networks through VLSI data compression. Wireless Networks 4(1): 27-39 (1998)
17EEYongjin Jeong, Wayne P. Burleson: VLSI array algorithms and architectures for RSA modular multiplication. IEEE Trans. VLSI Syst. 5(2): 211-217 (1997)
16EEMircea R. Stan, Wayne P. Burleson: Low-power encodings for global communication in CMOS VLSI. IEEE Trans. VLSI Syst. 5(4): 444-455 (1997)
15EEMircea R. Stan, Wayne P. Burleson: Two dimensional codes for low power. ISLPED 1996: 335-340
14EEZheng Zhou, Wayne Burleson: Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions. DAC 1995: 546-551
13EEMircea R. Stan, Wayne P. Burleson: Coding a terminated bus for low power. Great Lakes Symposium on VLSI 1995: 70-73
12 Yongjin Jeong, Wayne Burleson: High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding. ISCAS 1995: 720-723
11EEMircea R. Stan, Wayne P. Burleson: Bus-invert coding for low-power I/O. IEEE Trans. VLSI Syst. 3(1): 49-58 (1995)
10 Wayne Burleson: Using Regular Array Methods for DSP Module Synthesis. HICSS (1) 1994: 58-67
9 Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski: Forum: Wave-pipelining: Is it Practical? ISCAS 1994: 163-166
8 Bongjin Jung, Wayne Burleson: A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data Compression. ISCAS 1994: 65-68
7EEMircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen: Analog VLSI for robot path planning. VLSI Signal Processing 8(1): 61-73 (1994)
6 Wayne Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems: The Spring Scheduling Co-Processor: A Scheduling Accelerator. ICCD 1993: 140-144
5 Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems, Wayne Burleson, Jason Ko: The Spring Scheduling Co-Processor: Design, Use, and Performance. IEEE Real-Time Systems Symposium 1993: 106-111
4 J. David Narkiewicz, Wayne Burleson: Rank-order Filtering Algorithms: A Comparison of VLSI Implementations. ISCAS 1993: 1941-1944
3 Walter B. Marvin, Wayne Burleson: A Simulator for General Purpose Optical Arrays. ICCD 1991: 486-489
2 Wayne P. Burleson, Louis L. Scharf: Input/Output Design for VLSI Array Architectures. VLSI 1991: 357-366
1EEWayne P. Burleson, Louis L. Scharf: A VLSI design methodology for distributed arithmetic. VLSI Signal Processing 2(4): 235-252 (1991)

Coauthor Index

1Vikas Anand [40]
2Venkatesh Arunachalam [71]
3Ibis Benito [66]
4Lilian Bossuet [40] [48] [56] [61] [68]
5Jeevan Chittamuru [35] [51]
6Maciej J. Ciesielski [9] [22]
7Christopher I. Connolly [7]
8L. W. Cotten [9]
9Jean-Luc Danger [24] [29]
10Basab Datta [64] [69] [72] [73] [74] [75]
11Jean-Philippe Diguet [67] [68]
12Jeongseon Euh [27] [35] [51]
13Andrés D. García [24] [29]
14Dennis Goeckel [37] [45] [52]
15Guy Gogniat [40] [48] [56] [61] [62] [65] [67] [68]
16Roderic A. Grupen [7]
17Ian G. Harris [49] [54]
18Matthew W. Heath [49] [54]
19Prashant Jain [32] [45]
20Jinwook Jang [47] [58]
21David Jasinski [43] [53]
22Yongjin Jeong [12] [17]
23Bongjin Jung [8] [18] [20] [21]
24Fabian Klass [9] [22]
25Jason Ko [5] [6] [23]
26Konstantinos Konstantinides [19]
27Israel Koren [42]
28Hempraveen Kukkamalla [47]
29Andrew Laffely [38] [40] [41] [45] [47]
30C. Leonardo [28]
31Jian Liang [41]
32Lang Lin [70]
33W. Liu [22]
34Atul Maheshwari [36] [42] [44] [46] [50] [53] [59] [63]
35Elias S. Manolakos [26]
36Walter B. Marvin [3]
37Ankireddy Nalamalpu [33] [34]
38J. David Narkiewicz [4]
39Aiyappan Natarajan [43] [53] [59]
40Eduardo Wanderley Netto [65]
41Douglas Niehaus [5] [6] [23]
42S. R. Park [25]
43J. Peden [28]
44Jean Luc Philippe [40]
45Krithi Ramamritham [5] [6] [23]
46Ramaswamy Ramaswamy [52]
47Louis L. Scharf [1] [2]
48Naresh R. Shanbhag [31]
49Vijay Shankar [59]
50Sriram Srinivasan [34]
51Srividya Srinivasaraghavan [39]
52Mircea R. Stan [7] [11] [13] [15] [16]
53John A. Stankovic [5] [6] [23]
54Sriram Swaminathan [37] [52]
55Russell Tessier [30] [36] [37] [41] [43] [45] [46] [52] [53] [65] [67]
56Romain Vaslin [65] [67] [68]
57Subramanian Venkatraman [32]
58Vishak Venkatraman [47] [50] [55] [60]
59Gary Wallace [5] [6] [23]
60Charles C. Weems [5] [6] [23]
61Tilman Wolf [62] [68]
62Sheng Xu [57] [58] [66]
63Weifeng Xu [53]
64Zheng Zhou [14]
65Zhi Zhu [47]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)