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Pennsylvania State University
List of publications from the DBLP Bibliography Server - FAQother persons with the same name:
2009 | ||
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86 | EE | Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen: A novel architecture of the 3D stacked MRAM L2 cache for CMPs. HPCA 2009: 239-249 |
85 | EE | Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang: NBTI-aware statistical circuit delay assessment. ISQED 2009: 13-18 |
84 | EE | Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang: On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. ISQED 2009: 19-26 |
2008 | ||
83 | EE | Syed M. Alam, Mike Ignatowski, Yuan Xie: Technology, CAD tools, and designs for emerging 3D integration technology. ACM Great Lakes Symposium on VLSI 2008: 1-2 |
82 | EE | Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim: A low-power phase change memory based hybrid cache architecture. ACM Great Lakes Symposium on VLSI 2008: 395-398 |
81 | EE | Feng Wang, Xiaoxia Wu, Yuan Xie: Variability-driven module selection with joint design time optimization and post-silicon tuning. ASP-DAC 2008: 2-9 |
80 | EE | Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen: Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. DAC 2008: 554-559 |
79 | EE | Feng Wang, Guangyu Sun, Yuan Xie: A Variation Aware High Level Synthesis Framework. DATE 2008: 1063-1068 |
78 | EE | Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan: Thermal-aware reliability analysis for platform FPGAs. ICCAD 2008: 722-727 |
77 | EE | Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie: Comparative analysis of NBTI effects on low power and high performance flip-flops. ICCD 2008: 200-205 |
76 | EE | Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie: Test-access mechanism optimization for core-based three-dimensional SOCs. ICCD 2008: 212-218 |
75 | EE | Feng Wang, Yuan Xie: Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations. IPDPS 2008: 1-5 |
74 | EE | Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das: MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA 2008: 251-261 |
73 | EE | Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu: Hierarchical Soft Error Estimation Tool (HSEET). ISQED 2008: 680-683 |
72 | EE | Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam: Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. SASP 2008: 63-68 |
71 | EE | Jin Ouyang, Yuan Xie: Power optimization for FinFET-based circuits using genetic algorithms. SoCC 2008: 211-214 |
70 | EE | Yibo Chen, Jin Ouyang, Yuan Xie: ILP-based scheme for timing variation-aware scheduling and resource binding. SoCC 2008: 27-30 |
69 | EE | Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari: Toward Increasing FPGA Lifetime. IEEE Trans. Dependable Sec. Comput. 5(2): 115-127 (2008) |
68 | EE | Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Design Space Exploration for 3-D Cache. IEEE Trans. VLSI Syst. 16(4): 444-455 (2008) |
67 | EE | Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Case Study of Reliability-Aware and Low-Power Design. IEEE Trans. VLSI Syst. 16(7): 861-873 (2008) |
66 | EE | Yuan Xie, Jason Cong, Paul Franzon: Editorial: Special issue on 3D integrated circuits and microarchitectures. JETC 4(4): (2008) |
2007 | ||
65 | EE | Feng Wang, Yuan Xie, Hai Ju: A novel criticality computation method in statistical timing analysis. DATE 2007: 1611-1616 |
64 | EE | Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. DATE 2007: 546-551 |
63 | EE | Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan: Variation-aware task allocation and scheduling for MPSoC. ICCAD 2007: 598-603 |
62 | EE | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan: FPGA routing architecture analysis under variations. ICCD 2007: 152-157 |
61 | EE | Xiaoxia Wu, Paul Falkenstern, Yuan Xie: Scan chain design for three-dimensional integrated circuits (3D ICs). ICCD 2007: 208-214 |
60 | EE | Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das: A novel dimensionally-decomposed router for on-chip communication in 3D architectures. ISCA 2007: 138-149 |
59 | EE | Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: Modeling of PMOS NBTI Effect Considering Temperature Variation. ISQED 2007: 139-144 |
58 | EE | Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Analysis of CAM Cells. ISQED 2007: 333-338 |
57 | EE | Krishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Variation Impact on SER of Combinational Circuits. ISQED 2007: 911-916 |
56 | EE | Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie: A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. PATMOS 2007: 160-170 |
55 | EE | Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Architecting Microprocessor Components in 3D Design Space. VLSI Design 2007: 103-108 |
54 | EE | Feng Wang, Yuan Xie, R. Rajaraman, Balaji Vaidyanathan: Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. VLSI Design 2007: 165-170 |
53 | EE | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems CoRR abs/0710.4660: (2007) |
52 | EE | Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis CoRR abs/0710.4684: (2007) |
51 | EE | Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network CoRR abs/0710.4731: (2007) |
50 | EE | Gabriel H. Loh, Yuan Xie, Bryan Black: Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27(3): 31-48 (2007) |
49 | EE | Chang Hong Lin, Yuan Xie, Wayne Wolf: Code Compression for VLIW Embedded Systems Using a Self-Generating Table. IEEE Trans. VLSI Syst. 15(10): 1160-1171 (2007) |
48 | EE | Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Decompression Unit Design for VLIW Embedded Processors. IEEE Trans. VLSI Syst. 15(8): 975-980 (2007) |
47 | EE | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-aware Co-synthesis for Embedded Systems. VLSI Signal Processing 49(1): 87-99 (2007) |
2006 | ||
46 | EE | Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo: Leakage Optimized DECAP Design for FPGAs. APCCAS 2006: 960-963 |
45 | EE | Ozcan Ozturk, Feng Wang, Mahmut T. Kandemir, Yuan Xie: Optimal topology exploration for application-specific 3D architectures. ASP-DAC 2006: 390-395 |
44 | EE | Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari: FLAW: FPGA lifetime awareness. DAC 2006: 630-635 |
43 | EE | Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: On-chip bus thermal analysis and optimization. DATE 2006: 850-855 |
42 | EE | Wei-Lun Hung, Xiaoxia Wu, Yuan Xie: Guaranteeing performance yield in high-level synthesis. ICCAD 2006: 303-309 |
41 | EE | Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir: Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. ISCA 2006: 130-141 |
40 | EE | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ISQED 2006: 98-104 |
39 | EE | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie: Reliability-Aware SOC Voltage Islands Partition and Floorplan. ISVLSI 2006: 343-348 |
38 | EE | Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie: Delay and Energy Efficient Data Transmission for On-Chip Buses. ISVLSI 2006: 355-360 |
37 | EE | Feng Wang, Yuan Xie, Kerry Bernstein, Yan Luo: Dependability Analysis of Nano-scale FinFET circuits. ISVLSI 2006: 399-404 |
36 | EE | R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. VLSI Design 2006: 499-502 |
35 | EE | Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal: A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. VLSI Design 2006: 657-664 |
34 | EE | Narayanan Vijaykrishnan, Yuan Xie: Reliability Concerns in Embedded System Designs. IEEE Computer 39(1): 118-120 (2006) |
33 | EE | Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. IEEE Trans. VLSI Syst. 14(5): 525-536 (2006) |
32 | EE | Yuan Xie, Gabriel H. Loh, Bryan Black, Kerry Bernstein: Design space exploration for 3D architectures. JETC 2(2): 65-103 (2006) |
31 | EE | Yuan Xie, Wei-Lun Hung: Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design. VLSI Signal Processing 45(3): 177-189 (2006) |
2005 | ||
30 | EE | Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Designing reliable circuit in the presence of soft errors. ASP-DAC 2005: 1 |
29 | EE | Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie: Low-leakage robust SRAM cell design for sub-100nm technologies. ASP-DAC 2005: 539-544 |
28 | EE | John Conner, Yuan Xie, Mahmut T. Kandemir, Robert Dick, Greg M. Link: FD-HGAC: a hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection. ASP-DAC 2005: 709-712 |
27 | EE | Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie: Reliability-Centric High-Level Synthesis. DATE 2005: 1258-1263 |
26 | EE | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231 |
25 | EE | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. DATE 2005: 64-69 |
24 | EE | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin: Thermal-Aware Task Allocation and Scheduling for Embedded Systems. DATE 2005: 898-899 |
23 | EE | Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524 |
22 | EE | Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie: Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. ICCD 2005: 677-682 |
21 | EE | Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner: Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. ICCD 2005: 689-696 |
20 | EE | Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: An ILP Formulation for Reliability-Oriented High-Level Synthesis. ISQED 2005: 364-369 |
19 | EE | Suleyman Tosun, Nazanin Mansouri, Ercument Arvas, Mahmut T. Kandemir, Yuan Xie, Wei-Lun Hung: Reliability-Centric Hardware/Software Co-Design. ISQED 2005: 375-380 |
18 | EE | Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin: Thermal-Aware Floorplanning Using Genetic Algorithms. ISQED 2005: 634-639 |
17 | EE | Daniel Hostetler, Yuan Xie: Adaptive Power Management in Software Radios Using Resolution Adaptive Analog to Digital Converters. ISVLSI 2005: 186-191 |
16 | EE | Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang: Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. VLSI Design 2005: 165-170 |
15 | EE | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379 |
2004 | ||
14 | EE | Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: Design of a nanosensor array architecture. ACM Great Lakes Symposium on VLSI 2004: 298-303 |
13 | EE | Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin: Reliability-Aware Co-Synthesis for Embedded Systems. ASAP 2004: 41-50 |
12 | EE | Chang Hong Lin, Yuan Xie, Wayne Wolf: LZW-Based Code Compression for VLIW Embedded Systems. DATE 2004: 76-81 |
11 | EE | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin: Improving soft-error tolerance of FPGA configuration bits. ICCAD 2004: 107-110 |
10 | EE | Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin: Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. ICCD 2004: 430-437 |
9 | EE | Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin: The Effect of Threshold Voltages on the Soft Error Rate. ISQED 2004: 503-508 |
2003 | ||
8 | EE | Yuan Xie, Wayne Wolf, Haris Lekatsas: Profile-Driven Selective Code Compression. DATE 2003: 10462-10467 |
7 | EE | Yuan Xie, Wayne Wolf, Haris Lekatsas: Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. DCC 2003: 382-391 |
6 | EE | Yuan Xie, Jiang Xu, Wayne Wolf: Augmenting Platform-Based Design with Synthesis Tools. Journal of Circuits, Systems, and Computers 12(2): 125-142 (2003) |
2002 | ||
5 | EE | Haris Lekatsas, Wayne Wolf, Yuan Xie: Code Compression for VLIW Processors Using Variable-to-Fixed Coding. ISSS 2002: 138-143 |
2001 | ||
4 | EE | Yuan Xie, Wayne Wolf: Allocation and scheduling of conditional task graph in hardware/software co-synthesis. DATE 2001: 620-625 |
3 | EE | Yuan Xie, Haris Lekatsas, Wayne Wolf: Code Compression for VLIW Processors. Data Compression Conference 2001: 525 |
2 | EE | Yuan Xie, Wayne Wolf, Haris Lekatsas: A code decompression architecture for VLIW processors. MICRO 2001: 66-75 |
2000 | ||
1 | EE | Yuan Xie, Wayne Wolf: Co-synthesis with custom ASICs. ASP-DAC 2000: 129-134 |