Koji Nii

2009
11	EE	Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663
2008
10	EE	Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. VLSI Syst. 16(6): 620-627 (2008)
9	EE	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Transactions 91-C(4): 543-552 (2008)
2007
8	EE	Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112
7	EE	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Transactions 90-A(12): 2695-2702 (2007)
6	EE	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Transactions 90-C(10): 1949-1956 (2007)
2006
5	EE	Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto: A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66
4	EE	Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto: A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Transactions 89-A(12): 3634-3641 (2006)
2005
3		Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405
2	EE	Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino: A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76
1998
1	EE	Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano: A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED 1998: 293-298

Coauthor Index

1	Takahiko Arakawa	[1]
2	Hidehiro Fujiwara	[4] [5] [6] [7] [8] [9] [10] [11]
3	Hisanori Hamano	[1]
4	Yasushi Hayakawa	[1]
5	Yusuke Iguchi	[6] [7] [8] [9] [11]
6	Susumu Imaoka	[3]
7	Koichiro Ishibashi	[3]
8	Niichi Itoh	[2]
9	Hiroshi Kawaguchi	[4] [5] [6] [7] [8] [9] [10] [11]
10	Kentaro Kawakami	[4]
11	Hiroshi Makino	[1] [2] [3]
12	Shinji Mikami	[4]
13	Junichi Miyakoshi	[4] [5] [10]
14	Chikayoshi Morishima	[1]
15	Yasuhiro Morita	[4] [5] [6] [7] [8] [9] [10]
16	Yuichiro Murachi	[5] [10]
17	Hiroki Noguchi	[4] [6] [7] [8] [9] [10] [11]
18	Hiroyuki Nunogami	[1]
19	Yuji Oda	[3]
20	Shigeki Ohbayashi	[3]
21	Shunsuke Okumura	[9] [11]
22	Takeshi Shibagaki	[2]
23	Hirofumi Shinohara	[3]
24	Hidehiro Takata	[2]
25	Yasumasa Tsukamoto	[2] [3]
26	Yoshiki Tujihashi	[1]
27	Masahiko Yoshimoto	[4] [5] [6] [7] [8] [9] [10] [11]
28	Shusuke Yoshimoto	[11]
29	Tomoaki Yoshizawa	[3]