Li-Rong Zheng

2008
30	EE	Saul Rodriguez, Ana Rusu, Li-Rong Zheng, Mohammed Ismail: Digital calibration of gain and linearity in a CMOS RF mixer. ISCAS 2008: 1288-1291
29	EE	Linlin Zheng, Saul Rodriguez, Lu Zhang, Botao Shao, Li-Rong Zheng: Design and implementation of a fully reconfigurable chipless RFID tag using Inkjet printing technology. ISCAS 2008: 1524-1527
28	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. VLSI Syst. 16(5): 589-593 (2008)
27	EE	Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen: Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. IEEE Trans. VLSI Syst. 16(6): 766-770 (2008)
2007
26	EE	Yuechao Niu, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng: Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag. AINA Workshops (2) 2007: 358-361
25	EE	Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou: Traffic Splitting with Network Calculus for Mesh Sensor Networks. FGCN (2) 2007: 368-373
24	EE	Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD 2007: 212-219
23	EE	Majid Baghaei Nejad, Zhuo Zou, Hannu Tenhunen, Li-Rong Zheng: A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications. ISCAS 2007: 1593-1596
22	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design 2007: 308-313
2006
21	EE	Majid Baghaei Nejad, Li-Rong Zheng: An innovative receiver architecture for autonomous detection of ultra-wideband signals. ISCAS 2006
20	EE	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP 2006: 113-120
2005
19	EE	Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Case study of interconnect analysis for standing wave oscillator design. ISCAS (1) 2005: 456-459
18	EE	Xinzhong Duo, Li-Rong Zheng, Mohammed Ismail, Hannu Tenhunen: A concurrent multi-band LNA for multi-standard radios. ISCAS (4) 2005: 3982-3985
17	EE	Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. ISQED 2005: 573-578
16	EE	Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS 2005: 277-285
15	EE	Meigen Shen, Jian Liu, Li-Rong Zheng, Esa Tjukanoff, Hannu Tenhunen: Robustness enhancement through chip-package co-design for high-speed electronics. Microelectronics Journal 36(9): 846-855 (2005)
2004
14		Xinzhong Duo, Li-Rong Zheng, Hannu Tenhunen: RF robustness enhancement through statistical analysis of chip package co-design. ISCAS (1) 2004: 988-991
13	EE	Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics. ISQED 2004: 184-189
12	EE	Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen: A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integration 38(1): 3-17 (2004)
11	EE	Jian Liu, Li-Rong Zheng, Hannu Tenhunen: Interconnect intellectual property for Network-on-Chip (NoC). Journal of Systems Architecture 50(2-3): 65-79 (2004)
2003
10	EE	Wim Michielsen, Li-Rong Zheng, Hannu Tenhunen: Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio. ISCAS (1) 2003: 681-684
9	EE	Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen: A global wire planning scheme for Network-on-Chip. ISCAS (4) 2003: 892-895
8	EE	Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. ISCAS (5) 2003: 585-588
7	EE	Jian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen: System level interconnect design for network-on-chip using interconnect IPs. SLIP 2003: 117-124
6		Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch: Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC 2003: 362-
5	EE	Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. VLSI Syst. 11(2): 224-243 (2003)
4	EE	Li-Rong Zheng, Johan Liu: System-on-package: a broad perspective from system design to technology development. Microelectronics Reliability 43(8): 1339-1348 (2003)
2002
3	EE	Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen: Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) 2002: 193-196
1999
2	EE	Li-Rong Zheng, Hannu Tenhunen: Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits. ARVLSI 1999: 123-136
1	EE	Li-Rong Zheng, Hannu Tenhunen: Effective power and ground distribution scheme for deep submicron high speed VLSI circuits. ISCAS (1) 1999: 537-540

Coauthor Index

1	Xinzhong Duo	[14] [18]
2	Mohammed Ismail	[18] [30]
3	Jouni Isoaho	[17] [19] [27]
4	Axel Jantsch	[6] [12] [25]
5	Jian Liu	[7] [9] [11] [15]
6	Johan Liu	[4]
7	Zhonghai Lu	[25]
8	Wim Michielsen	[10]
9	Mikael Millberg	[6] [12]
10	Majid Baghaei Nejad	[21] [23] [26]
11	Yuechao Niu	[26]
12	Johnny Öberg	[6] [12]
13	Dinesh Pamunuwa	[3] [5] [6] [9] [12] [16] [20] [22] [24] [28]
14	Saul Rodriguez	[29] [30]
15	Ana Rusu	[30]
16	Botao Shao	[29]
17	Huimin She	[25]
18	Meigen Shen	[7] [8] [13] [15] [17] [19]
19	Hannu Tenhunen	[1] [2] [3] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [22] [23] [24] [26] [27] [28]
20	Esa Tjukanoff	[15] [17] [19]
21	Sampo Tuuna	[27]
22	Roshan Weerasekera	[16] [20] [22] [24] [28]
23	Lu Zhang	[29]
24	Linlin Zheng	[29]
25	Dian Zhou	[25]
26	Zhuo Zou	[23]

Colors in the list of coauthors