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Ling Zhuo

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2008
22EELing Zhuo, Qingbo Wang, Viktor K. Prasanna: Matrix Computations on Heterogeneous Reconfigurable Systems. FCCM 2008: 310-311
21EELing Zhuo, Viktor K. Prasanna: Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems. IEEE Trans. Computers 57(12): 1661-1675 (2008)
20EELing Zhuo, Viktor K. Prasanna: High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware. IEEE Trans. Computers 57(8): 1057-1071 (2008)
19EERonald Scrofano, Ling Zhuo, Viktor K. Prasanna: Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores. IEEE Trans. VLSI Syst. 16(2): 167-176 (2008)
2007
18EELing Zhuo, Viktor K. Prasanna: Hardware/Software Co-Design for Matrix Computations on Reconfigurable Computing Systems. IPDPS 2007: 1-10
17 Ling Zhuo, Viktor K. Prasanna: Optimizing Matrix Multiplication on Heterogeneous Reconfigurable Systems. PARCO 2007: 561-568
16EELing Zhuo, Gerald R. Morris, Viktor K. Prasanna: High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. IEEE Trans. Parallel Distrib. Syst. 18(10): 1377-1392 (2007)
15EELing Zhuo, Viktor K. Prasanna: Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems. IEEE Trans. Parallel Distrib. Syst. 18(4): 433-448 (2007)
2006
14EELing Zhuo, Viktor K. Prasanna: High-Performance and Parameterized Matrix Factorization on FPGAs. FPL 2006: 1-6
13EELing Zhuo, Viktor K. Prasanna: Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems. ICPADS (1) 2006: 87-95
2005
12 Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna: Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores. ERSA 2005: 119-128
11EEGerald R. Morris, Ling Zhuo, Viktor K. Prasanna: High-Performance FPGA-Based General Reduction Methods. FCCM 2005: 323-324
10EELing Zhuo, Viktor K. Prasanna: Sparse Matrix-Vector multiplication on FPGAs. FPGA 2005: 63-74
9EELing Zhuo, Viktor K. Prasanna: Design Tradeoffs for BLAS Operations on Reconfigurable Hardware. ICPP 2005: 78-86
8EELing Zhuo, Gerald R. Morris, Viktor K. Prasanna: Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. IPDPS 2005
7EELing Zhuo, Viktor K. Prasanna: High-Performance and Area-Efficient Reduction Circuits on FPGAs. SBAC-PAD 2005: 52-59
6EELing Zhuo, Viktor K. Prasanna: High Performance Linear Algebra Operations on Reconfigurable Systems. SC 2005: 2
2004
5 Ling Zhuo, Viktor K. Prasanna: Energy Performance of Floating-Point Matrix Multiplication on FPGAs. ERSA 2004: 316
4EEGokul Govindu, Ling Zhuo, Seonil Choi, Viktor K. Prasanna: Analysis of High-Performance Floating-Point Arithmetic on FPGAs. IPDPS 2004
3EELing Zhuo, Viktor K. Prasanna: Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on FPGAs. IPDPS 2004
2003
2EELing Zhuo, Cho-Li Wang, Francis C. M. Lau: Document replication and distribution in extensible geographically distributed web servers. J. Parallel Distrib. Comput. 63(10): 927-944 (2003)
2002
1EELing Zhuo, Cho-Li Wang, Francis C. M. Lau: Load Balancing in Distributed Web Server Systems with Partial Document Replication. ICPP 2002: 305-

Coauthor Index

1Seonil Choi [4]
2Gokul Govindu [4]
3Francis Chi-Moon Lau (Francis C. M. Lau) [1] [2]
4Gerald R. Morris [8] [11] [16]
5Viktor K. Prasanna (V. K. Prasanna Kumar) [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]
6Ronald Scrofano [12] [19]
7Cho-Li Wang [1] [2]
8Qingbo Wang [22]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)