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Mihalis Psarakis

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2009
27EEGeorge Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units. IEEE Trans. Dependable Sec. Comput. 6(2): 124-134 (2009)
2008
26EEA. Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Functional Self-Testing for Bus-Based Symmetric Multiprocessors. DATE 2008: 1304-1309
25EEDimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. VLSI Syst. 16(11): 1441-1453 (2008)
2007
24EEGeorge Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. DFT 2007: 379-387
23EEA. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. IOLTS 2007: 271-276
22EEA. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. IEEE Trans. VLSI Syst. 15(8): 971-975 (2007)
2006
21EEMihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi: Systematic software-based self-test for pipelined processors. DAC 2006: 393-398
20EEP. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis: A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. IOLTS 2006: 235-241
19EEGeorge Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. IEEE Trans. Computers 55(11): 1449-1457 (2006)
2005
18EEMiltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis: Software-Based Self-Test for Pipelined Processors: A Case Study. DFT 2005: 535-543
17EEGeorge Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Test Generation Methodology for High-Speed Floating Point Adders. IOLTS 2005: 227-232
16EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Built-in sequential fault self-testing of array multipliers. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 449-460 (2005)
2003
15EEDimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Easily Testable Cellular Carry Lookahead Adders. J. Electronic Testing 19(3): 285-298 (2003)
2001
14EEAntonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian: Deterministic software-based self-testing of embedded processor cores. DATE 2001: 92-96
13EENektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. ISQED 2001: 343-349
12EEMihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian: Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. VTS 2001: 15-21
11EENektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis, Yervant Zorian: An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. J. Electronic Testing 17(2): 97-107 (2001)
2000
10EEDimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Effective Low Power BIST for Datapaths. DATE 2000: 757
9EEDimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian: Low Power/Energy BIST Scheme for Datapaths. VTS 2000: 23-28
8EENektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian: Power-/Energy Efficient BIST Schemes for Processor Data Paths. IEEE Design & Test of Computers 17(4): 15-28 (2000)
7EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. IEEE Trans. Computers 49(10): 1083-1099 (2000)
1999
6EEAntonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Fast Multiplier Cores. DATE 1999: 117-121
5EEMihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian: An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. VTS 1999: 252-259
1998
4EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian: Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. VTS 1998: 152-157
3EEMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools. J. Electronic Testing 13(3): 315-319 (1998)
1997
2 Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis: An Effective BIST Scheme for Arithmetic Logic Units. ITC 1997: 868-877
1EEDimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis: Robust Sequential Fault Testing of Iterative Logic Arrays. VTS 1997: 238-244

Coauthor Index

1A. Apostolakis [22] [23] [26]
2Dimitris Gizopoulos [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
3Miltiadis Hatzimihail [18] [21] [25]
4P. Kenterlis [20]
5Nektarios Kranitis [6] [8] [9] [10] [11] [12] [13] [14] [20]
6M. Maniatakos [25]
7Antonis M. Paschalis [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
8Anand Raghunathan [21] [25]
9Srivaths Ravi [21] [25]
10George Xenoulis [17] [18] [19] [24] [27]
11Yervant Zorian [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)