Steven J. E. Wilton

2009
54	EE	Alastair M. Smith, Steven J. E. Wilton, Joydip Das: Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA 2009: 181-190
53	EE	Scott Y. L. Chin, Steven J. E. Wilton: Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. TRETS 1(4): (2009)
2008
52	EE	Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk: An analytical model describing the relationships between logic architecture and FPGA density. FPL 2008: 221-226
51	EE	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Rapid estimation of power consumption for hybrid FPGAs. FPL 2008: 227-232
50	EE	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
49	EE	Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Practical Asynchronous Interconnect Network Design. IEEE Trans. VLSI Syst. 16(5): 579-588 (2008)
48	EE	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk: A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. TRETS 1(1): (2008)
47	EE	Julien Lamoureux, Steven J. E. Wilton: On the trade-off between power and flexibility of FPGA clock networks. TRETS 1(3): (2008)
2007
46	EE	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
45	EE	Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton: A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41
44	EE	Julien Lamoureux, Steven J. E. Wilton: Clock-Aware Placement for FPGAs. FPL 2007: 124-131
43	EE	Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL 2007: 196-201
42	EE	Bradley R. Quinton, Steven J. E. Wilton: Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL 2007: 202-209
2006
41		Steven J. E. Wilton, André DeHon: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 ACM 2006
40	EE	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo: Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM 2006: 35-44
39	EE	Julien Lamoureux, Steven J. E. Wilton: FPGA clock network architecture: flexibility vs. area and power. FPGA 2006: 101-108
38	EE	Julien Lamoureux, Steven J. E. Wilton: Architecture and CAD for FPGA Clock Networks. FPL 2006: 1-2
37	EE	Julien Lamoureux, Steven J. E. Wilton: Activity Estimation for Field-Programmable Gate Arrays. FPL 2006: 1-8
36	EE	Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton: Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL 2006: 1-8
35	EE	Andy Yan, Steven J. E. Wilton: Product-Term-Based Synthesizable Embedded Programmable Logic Cores. IEEE Trans. VLSI Syst. 14(5): 474-488 (2006)
2005
34		Herman Schmit, Steven J. E. Wilton: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005 ACM 2005
33		Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong: Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005 IEEE 2005
32	EE	Zion Kwok, Steven J. E. Wilton: Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. FCCM 2005: 35-44
31		C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Dynamic Voltage Scaling for Commercial FPGAs. FPT 2005: 173-180
30		Bradley R. Quinton, Steven J. E. Wilton: Post-Silicon Debug Using Programmable Logic Cores. FPT 2005: 241-248
29	EE	Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274
28	EE	Bradley R. Quinton, Steven J. E. Wilton: Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) 2005: 45-48
27	EE	Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton: Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90
26	EE	Kara K. W. Poon, Steven J. E. Wilton, Andy Yan: A detailed power model for field-programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 10(2): 279-302 (2005)
25	EE	Peter Hallschmid, Steven J. E. Wilton: Routing architecture optimizations for high-density embedded programmable IP cores. IEEE Trans. VLSI Syst. 13(11): 1320-1324 (2005)
24	EE	S. W. Oldridge, Steven J. E. Wilton: A novel FPGA architecture supporting wide, shallow memories. IEEE Trans. VLSI Syst. 13(6): 758-762 (2005)
23	EE	Julien Lamoureux, Steven J. E. Wilton: On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electronics 1(2): 119-132 (2005)
2004
22	EE	Steven J. E. Wilton, Su-Shin Ang, Wayne Luk: The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL 2004: 719-728
21		Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux: An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) 2004: 885-888
2003
20	EE	Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton: Architectures and algorithms for synthesizable embedded programmable logic cores. FPGA 2003: 3-11
19	EE	Julien Lamoureux, Steven J. E. Wilton: On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD 2003: 701-708
2002
18	EE	Andy Yan, Rebecca Cheng, Steven J. E. Wilton: On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. FPGA 2002: 147-156
17	EE	Kara K. W. Poon, Andy Yan, Steven J. E. Wilton: A Flexible Power Model for FPGAs. FPL 2002: 312-321
2001
16	EE	Steven J. E. Wilton: A crosstalk-aware timing-driven router for FPGAs. FPGA 2001: 21-28
15	EE	Peter Hallschmid, Steven J. E. Wilton: Detailed routing architectures for embedded programmable logic IP cores. FPGA 2001: 69-74
14	EE	Ernie Lin, Steven J. E. Wilton: Macrocell Architectures for Product Term Embedded Memory Arrays. FPL 2001: 48-58
13	EE	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. VLSI Syst. 9(1): 223-226 (2001)
2000
12	EE	Steven J. E. Wilton: Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. FPGA 2000: 67-74
11	EE	Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh: FPGA Implementation of a Prototype WDM On-Line Scheduler. FPL 2000: 773-776
10	EE	Steven J. E. Wilton: Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 56-68 (2000)
1999
9		William K. C. Ho, Steven J. E. Wilton: Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. FPL 1999: 111-123
8		M. Imran Masud, Steven J. E. Wilton: A New Switch Block for Segmented FPGAs. FPL 1999: 274-281
7	EE	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. VLSI Syst. 7(1): 80-91 (1999)
1998
6	EE	Steven J. E. Wilton: SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. FPGA 1998: 171-178
1997
5	EE	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16
1995
4	EE	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic: Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103
1994
3		Norman P. Jouppi, Steven J. E. Wilton: Tradeoffs in Two-Level On-Chip Caching. ISCA 1994: 34-45
1993
2		Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton: A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948
1		Steven J. E. Wilton, Zvonko G. Vranesic: Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP 1993: 51-55

Coauthor Index

1	Su-Shin Ang	[22]
2	Kimberly Bozman	[20]
3	John Chappel	[2]
4	Rebecca Cheng	[18]
5	Winnie W. Cheng	[11]
6	Scott Y. L. Chin	[36] [53]
7	C. T. Chow	[31]
8	Paul Chow	[2]
9	Joydip Das	[54]
10	André DeHon	[41]
11	Gennady Feygin	[2]
12	Grant Goodes	[2]
13	Mark R. Greenstreet	[29] [49]
14	P. Glenn Gulak	[2]
15	Oswin Hall	[2]
16	Peter Hallschmid	[15] [25]
17	Babak Hamidzadeh	[11]
18	Lei He	[27]
19	Chun Hok Ho	[40] [43] [45] [48] [51]
20	William K. C. Ho	[9]
21	Michael Hutton (Michael D. Hutton, Mike Hutton)	[27]
22	Christopher W. Jones	[21]
23	Norman P. Jouppi	[3]
24	Noha Kafafi	[20]
25	Zion Kwok	[32]
26	Andrew Lam	[52]
27	Julien Lamoureux	[19] [21] [23] [37] [38] [39] [44] [46] [47] [50]
28	Clarence S. P. Lee	[36]
29	Guy G. Lemieux	[46] [50]
30	Philip Heng Wai Leong	[31] [33] [40] [43] [45] [48] [51] [52]
31	Ernie Lin	[14]
32	Sergio López-Buedo	[40]
33	Wayne Luk	[22] [31] [40] [43] [45] [48] [51] [52]
34	M. Imran Masud	[8]
35	S. W. Oldridge	[24]
36	Kara K. W. Poon	[17] [26]
37	Bradley R. Quinton	[28] [29] [30] [42] [45] [48] [49]
38	Tero Rissa	[33]
39	Jonathan Rose	[4] [5] [7] [13]
40	Ahmad Sayes	[2]
41	Herman Schmit	[34]
42	Satwant Singh	[2]
43	Alastair M. Smith	[54]
44	Michael B. Smith	[2]
45	L. S. M. Tsui	[31]
46	Tim Tuan	[27]
47	Zvonko G. Vranesic	[1] [4] [5] [7] [13]
48	Andy Yan	[17] [18] [26] [35]
49	Chi Wai Yu	[43]

Colors in the list of coauthors