Joseph J. Sharkey

2008
19	EE	Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose: Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. IEEE Trans. Computers 57(1): 82-95 (2008)
18	EE	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose: Selective Writeback: Reducing Register File Pressure and Energy Consumption. IEEE Trans. VLSI Syst. 16(6): 650-661 (2008)
17	EE	Joseph J. Sharkey, Jason Loew, Dmitry V. Ponomarev: Reducing register pressure in SMT processors through L2-miss-driven early register release. TACO 5(3): (2008)
2007
16	EE	Joseph J. Sharkey, Dmitry V. Ponomarev: An L2-miss-driven early register deallocation for SMT processors. ICS 2007: 138-147
15	EE	Joseph J. Sharkey, Alper Buyuktosunoglu, Pradip Bose: Evaluating design tradeoffs in on-chip power management for CMPs. ISLPED 2007: 44-49
14	EE	Joseph J. Sharkey, Dmitry V. Ponomarev: Exploiting Operand Availability for Efficient Simultaneous Multithreading. IEEE Trans. Computers 56(2): 208-223 (2007)
2006
13	EE	Joseph J. Sharkey, Dmitry V. Ponomarev: Efficient instruction schedulers for SMT processors. HPCA 2006: 288-298
12	EE	Joseph J. Sharkey, Nayef Abu-Ghazeleh, Dmitry V. Ponomarev, Kanad Ghose, Aneesh Aggarwal: Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors. HiPC 2006: 135-147
11	EE	Joseph J. Sharkey, Dmitry Ponomarev: Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch. ICPP 2006: 329-336
10	EE	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Aneesh Aggarwal: Address-Value Decoupling for Early Register Deallocation. ICPP 2006: 337-346
9	EE	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose: Selective writeback: exploiting transient values for energy-efficiency and performance. ISLPED 2006: 37-42
8	EE	Joseph J. Sharkey, Deniz Balkan, Dmitry Ponomarev: Adaptive reorder buffers for SMT processors. PACT 2006: 244-253
7	EE	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose: SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency. PACT 2006: 265-274
6	EE	Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin: Instruction packing: Toward fast and energy-efficient instruction scheduling. TACO 3(2): 156-181 (2006)
2005
5	EE	Joseph J. Sharkey, Dmitry V. Ponomarev: Non-uniform Instruction Scheduling. Euro-Par 2005: 540-549
4	EE	Joseph J. Sharkey, Dmitry V. Ponomarev: Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers. Euro-Par 2005: 550-559
3	EE	Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin: Power-Efficient Wakeup Tag Broadcast. ICCD 2005: 654-661
2	EE	Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin: Instruction packing: reducing power and delay of the dynamic scheduling logic. ISLPED 2005: 30-35
2004
1	EE	Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin: Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. PACS 2004: 15-29

Coauthor Index

1	Nayef Abu-Ghazeleh	[12]
2	Aneesh Aggarwal	[10] [12]
3	Deniz Balkan	[7] [8] [9] [10] [18] [19]
4	Pradip Bose	[15]
5	Alper Buyuktosunoglu	[15]
6	Oguz Ergin	[1] [2] [3] [6]
7	Kanad Ghose	[1] [2] [3] [6] [7] [9] [12] [18] [19]
8	Jason Loew	[17]
9	Dmitry V. Ponomarev (Dmitry Ponomarev)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [18] [19]