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Arifur Rahman

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2008
6EEAman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman: Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Trans. VLSI Syst. 16(7): 882-893 (2008)
2004
5EEArifur Rahman, Vijay Polavarapuv: Evaluation of low-leakage design techniques for field programmable gate arrays. FPGA 2004: 23-30
2003
4 Arifur Rahman: Models for Full-Chip Power Dissipation in Field Programmable Gate Arrays and the Impact of Subthreshold Leakage Current. VLSI 2003: 97-106
3EEArifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif: Wiring requirement and three-dimensional integration technology for field programmable gate arrays. IEEE Trans. VLSI Syst. 11(1): 44-54 (2003)
2001
2EEArifur Rahman, Shamik Das, Anantha Chandrakasan, Rafael Reif: Wiring requirement and three-dimensional integration of field-programmable gate arrays. SLIP 2001: 107-113
2000
1EEArifur Rahman, Rafael Reif: System-level performance evaluation of three-dimensional integrated circuits. IEEE Trans. VLSI Syst. 8(6): 671-678 (2000)

Coauthor Index

1Anantha Chandrakasan (Anantha P. Chandrakasan) [2] [3]
2Shamik Das [2] [3]
3Aman Gayasen [6]
4Mahmut T. Kandemir [6]
5Vijay Polavarapuv [5]
6Rafael Reif [1] [2] [3]
7Narayanan Vijaykrishnan (Vijaykrishnan Narayanan) [6]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)