| 2008 |
|---|
| 12 | EE | Takefumi Yoshikawa,
T. Hirata,
Tsuyoshi Ebuchi,
Toru Iwata,
Yukio Arima,
Hiroyuki Yamauchi:
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.
IEEE Trans. VLSI Syst. 16(9): 1187-1198 (2008) |
| 2007 |
|---|
| 11 | EE | Hiroyuki Yamauchi,
Toshikazu Suzuki,
Yoshinobu Yamagami:
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses.
IEICE Transactions 90-C(4): 749-757 (2007) |
| 10 | EE | Yasue Yamamoto,
Masanori Shirahama,
Toshiaki Kawasaki,
Ryuji Nishihara,
Shinichi Sumi,
Yasuhiro Agata,
Hirohito Kikukawa,
Hiroyuki Yamauchi:
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
IEICE Transactions 90-C(5): 1129-1137 (2007) |
| 2006 |
|---|
| 9 | EE | Hiroyuki Yamauchi,
Toshikazu Suzuki,
Yoshinobu Yamagami:
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation.
IEICE Transactions 89-C(11): 1526-1534 (2006) |
| 2005 |
|---|
| 8 | EE | Toshikazu Suzuki,
Yoshinobu Yamagami,
Ichiro Hatanaka,
Akinori Shibayama,
Hironori Akamatsu,
Hiroyuki Yamauchi:
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.
IEICE Transactions 88-C(4): 630-638 (2005) |
| 2000 |
|---|
| 7 | EE | Hiroyuki Yamauchi,
Setsuo Ohsuga:
A Method and Language for Constructing Multiagent Systems.
ISMIS 2000: 619-628 |
| 1999 |
|---|
| 6 | | Hiroyuki Yamauchi,
Setsuo Ohsuga:
Incorporating Fuzzy Set Theory and Matrix Logic in Multi-Layer Logic - A Preliminary Consideration.
RSFDGrC 1999: 304-313 |
| 1997 |
|---|
| 5 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.
IEEE Trans. VLSI Syst. 5(4): 377-387 (1997) |
| 1996 |
|---|
| 4 | EE | Hiroyuki Yamauchi,
Toru Iwata,
Hironori Akamatsu,
Akira Matsuzawa:
A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.
ISLPED 1996: 49-54 |
| 1990 |
|---|
| 3 | | Hiroyuki Yamauchi,
Setsuo Ohsuga:
Losse Coupling of KAUS with Existing RDBMSs.
Data Knowl. Eng. 5: 227-251 (1990) |
| 1985 |
|---|
| 2 | | Setsuo Ohsuga,
Hiroyuki Yamauchi:
Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language.
New Generation Comput. 3(4): 403-439 (1985) |
| 1980 |
|---|
| 1 | EE | Hiroyuki Yamauchi:
Processing Of Syntax And Semantics Of Natural Language By Predicate Logic Of Predicate Logic.
COLING 1980: 389-396 |
