| 2008 |
|---|
| 9 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.
VLSI Design 2008: 572-579 |
| 8 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.
VLSI Design 2008: 635-640 |
| 7 | EE | Sabyasachi Das,
Sunil P. Khatri:
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.
VLSI Design 2008: 653-659 |
| 6 | EE | Sabyasachi Das,
Sunil P. Khatri:
Resource sharing among mutually exclusive sum-of-product blocks for area reduction.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 5 | EE | Sabyasachi Das,
Sunil P. Khatri:
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.
IEEE Trans. VLSI Syst. 16(3): 326-331 (2008) |
| 2006 |
|---|
| 4 | EE | Sabyasachi Das,
Sandip Paul,
Chitra Dutta:
Trends in Codon and Amino Acid Usage in Human Pathogen Tropheryma Whipplei, the only Known Actinobacteria with Reduced Genome.
APBC 2006: 139-148 |
| 3 | EE | Sandip Paul,
Sabyasachi Das,
Chitra Dutta:
Consequences of Mutation, Selection, and Physico-Chemical Properties of Encoded Proteins on Synonymous Codon Usage in Adenoviruses.
APBC 2006: 149-158 |
| 2002 |
|---|
| 2 | EE | Sabyasachi Das,
Sunil P. Khatri:
An efficient and regular routing methodology for datapath designsusing net regularity extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 93-101 (2002) |
| 2001 |
|---|
| 1 | EE | Sabyasachi Das,
Sunil P. Khatri:
A regularity-driven fast gridless detailed router for high frequency datapath designs.
ISPD 2001: 130-135 |
