| 2009 |
|---|
| 97 | EE | Torsten Kempf,
Stefan Wallentowitz,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios.
VLSI Design 2009: 281-286 |
| 96 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
| 95 | EE | Manuel Hohenauer,
Felix Engel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
A SIMD optimization framework for retargetable compilers.
TACO 6(1): (2009) |
| 2008 |
|---|
| 94 | EE | Lei Gao,
Kingshuk Karuri,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Multiprocessor performance estimation using hybrid simulation.
DAC 2008: 325-330 |
| 93 | EE | Jianjiang Ceng,
Jerónimo Castrillón,
Weihua Sheng,
Hanno Scharwächter,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tsuyoshi Isshiki,
Hiroaki Kunieda:
MAPS: an integrated framework for MPSoC application parallelization.
DAC 2008: 754-759 |
| 92 | EE | Anupam Chattopadhyay,
Xiaolin Chen,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures.
DATE 2008: 1334-1339 |
| 91 | EE | Manuel Hohenauer,
Felix Engel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gerrit Bette,
Balpreet Singh:
Retargetable Code Optimization for Predicated Execution.
DATE 2008: 1492-1497 |
| 90 | EE | I-Wei Lai,
Susanne Godtmann,
Tzi-Dar Chiueh,
Gerd Ascheid,
Heinrich Meyr:
Asymptotic BER Analysis for MIMO-BICM with Zero-Forcing Detectors Assuming Imperfect CSI.
ICC 2008: 1238-1242 |
| 89 | EE | Markus Jordan,
Martin Senst,
Gerd Ascheid,
Heinrich Meyr:
Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation.
VTC Spring 2008: 275-279 |
| 88 | EE | Anupam Chattopadhyay,
Harold Ishebabi,
Xiaolin Chen,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.
ACM Trans. Embedded Comput. Syst. 7(4): (2008) |
| 87 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Xiaolin Chen,
David Kammler,
Ling Hao,
Rainer Leupers,
Heinrich Meyr,
Gerd Ascheid:
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.
IEEE Trans. VLSI Syst. 16(10): 1281-1294 (2008) |
| 86 | EE | Andreas Wieferink,
Tim Kogel,
Olaf Zerres,
Rainer Leupers,
Heinrich Meyr:
SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends.
IJES 3(3): 109-118 (2008) |
| 85 | EE | Tim Kogel,
Malte Doerper,
Torsten Kempf,
Andreas Wieferink,
Rainer Leupers,
Heinrich Meyr:
Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips.
IJES 3(3): 150-159 (2008) |
| 84 | EE | Diandian Zhang,
Anupam Chattopadhyay,
David Kammler,
Ernst Martin Witte,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes.
JCP 3(3): 25-38 (2008) |
| 2007 |
|---|
| 83 | EE | Lei Gao,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
A fast and generic hybrid simulation approach using C virtual machine.
CASES 2007: 3-12 |
| 82 | EE | Hanno Scharwächter,
Jonghee M. Yoon,
Rainer Leupers,
Yunheung Paek,
Gerd Ascheid,
Heinrich Meyr:
A code-generator generator for multi-output instructions.
CODES+ISSS 2007: 131-136 |
| 81 | EE | Stefan Kraemer,
Lei Gao,
Jan Weinstock,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
HySim: a fast simulation framework for embedded software development.
CODES+ISSS 2007: 75-80 |
| 80 | EE | Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations.
DATE 2007: 1349-1354 |
| 79 | EE | Anupam Chattopadhyay,
W. Ahmed,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Design space exploration of partially re-configurable embedded processors.
DATE 2007: 319-324 |
| 78 | EE | Martin Senst,
Markus Jordan,
Meik Dorpinghaus,
Michael Farber,
Gerd Ascheid,
Heinrich Meyr:
Joint Reduction of Peak-to-Average Power Ratio and Out-of-Band Power in OFDM Systems.
GLOBECOM 2007: 3812-3816 |
| 77 | EE | Kingshuk Karuri,
Anupam Chattopadhyay,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Increasing data-bandwidth to instruction-set extensions through register clustering.
ICCAD 2007: 166-171 |
| 76 | EE | Anupam Chattopadhyay,
Z. Rakosi,
Kingshuk Karuri,
David Kammler,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.
IEEE International Workshop on Rapid System Prototyping 2007: 189-194 |
| 75 | EE | Markus Jordan,
Gerd Ascheid,
Heinrich Meyr:
Performance Evaluation of Opportunistic Beamforming with SINR Prediction for HSDPA.
VTC Spring 2007: 1652-1656 |
| 74 | EE | Susanne Godtmann,
André Pollok,
Niels Hadaschik,
Gerd Ascheid,
Heinrich Meyr:
On the Influence of Pilot Symbol and Data Symbol Positioning on Turbo Synchronization.
VTC Spring 2007: 1723-1726 |
| 73 | EE | Hanno Scharwächter,
David Kammler,
Andreas Wieferink,
Manuel Hohenauer,
Kingshuk Karuri,
Jianjiang Ceng,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
ASIP architecture exploration for efficient IPSec encryption: A case study.
ACM Trans. Embedded Comput. Syst. 6(2): (2007) |
| 2006 |
|---|
| 72 | EE | Manuel Hohenauer,
Christoph Schumacher,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Hans van Someren:
Retargetable code optimization with SIMD instructions.
CODES+ISSS 2006: 148-153 |
| 71 | EE | Torsten Kempf,
Kingshuk Karuri,
Stefan Wallentowitz,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
A SW performance estimation framework for early system-level-design using fine-grained instrumentation.
DATE 2006: 468-473 |
| 70 | EE | Anupam Chattopadhyay,
B. Geukes,
David Kammler,
Ernst Martin Witte,
Oliver Schliebusch,
Harold Ishebabi,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors.
DATE 2006: 600-605 |
| 69 | EE | Hanno Scharwächter,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
An interprocedural code optimization technique for network processors using hardware multi-threading support.
DATE 2006: 919-924 |
| 68 | EE | Kingshuk Karuri,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Monu Kedia:
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.
DATE Designers' Forum 2006: 221-226 |
| 67 | EE | Luca Fanucci,
Michele Cassiano,
Sergio Saponara,
David Kammler,
Ernst Martin Witte,
Oliver Schliebusch,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing.
DATE Designers' Forum 2006: 233-238 |
| 66 | EE | Kingshuk Karuri,
Christian Huben,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Memory Access Micro-Profiling for ASIP Design.
DELTA 2006: 255-262 |
| 65 | EE | Anupam Chattopadhyay,
Arnab Sinha,
Diandian Zhang,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design.
IEEE International Workshop on Rapid System Prototyping 2006: 110-118 |
| 64 | EE | Harold Ishebabi,
Gerd Ascheid,
Heinrich Meyr,
O. Atak,
A. Atalar,
E. Arikan:
An efficient parallelization technique for high throughput FFT-ASIPs.
ISCAS 2006 |
| 63 | EE | Peter Wintermayr,
Reiner W. Hartenstein,
Heinrich Meyr,
Steve Leibson:
Flexibility and low power: a contradiction in terms?
ISLPED 2006: 375 |
| 62 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
VLSI Signal Processing 43(2-3): 235-246 (2006) |
| 2005 |
|---|
| 61 | EE | Mohammad Mostafizur Rahman Mozumdar,
Kingshuk Karuri,
Anupam Chattopadhyay,
Stefan Kraemer,
Hanno Scharwächter,
Heinrich Meyr,
Gerd Ascheid,
Rainer Leupers:
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.
ASAP 2005: 154-160 |
| 60 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr,
Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages.
ASP-DAC 2005: 280-285 |
| 59 | EE | Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tom Michiels,
Achim Nohl,
Tim Kogel:
Retargetable generation of TLM bus interfaces for MP-SoC platforms.
CODES+ISSS 2005: 249-254 |
| 58 | EE | Kingshuk Karuri,
Mohammad Abdullah Al Faruque,
Stefan Kraemer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Fine-grained application source code profiling for ASIP design.
DAC 2005: 329-334 |
| 57 | EE | Jianjiang Ceng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
C Compiler Retargeting Based on Instruction Semantics Models.
DATE 2005: 1150-1155 |
| 56 | EE | Torsten Kempf,
Malte Doerper,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Tim Kogel,
Bart Vanthournout:
A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms.
DATE 2005: 876-881 |
| 55 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Ernst Martin Witte,
David Kammler,
Gerd Ascheid,
Rainer Leupers,
Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis.
IEEE International Workshop on Rapid System Prototyping 2005: 165-171 |
| 2004 |
|---|
| 54 | EE | Tim Kogel,
Heinrich Meyr:
Heterogeneous MP-SoC: the solution to energy-efficient signal processing.
DAC 2004: 686-691 |
| 53 | EE | Gunnar Braun,
Achim Nohl,
Weihua Sheng,
Jianjiang Ceng,
Manuel Hohenauer,
Hanno Scharwächter,
Rainer Leupers,
Heinrich Meyr:
A novel approach for flexible and consistent ADL-driven ASIP design.
DAC 2004: 717-722 |
| 52 | EE | Andreas Wieferink,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Achim Nohl:
A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform.
DATE 2004: 1256-1263 |
| 51 | EE | Manuel Hohenauer,
Hanno Scharwächter,
Kingshuk Karuri,
Oliver Wahlen,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun,
Hans van Someren:
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models.
DATE 2004: 1276-1283 |
| 50 | EE | Oliver Schliebusch,
Anupam Chattopadhyay,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Mario Steinert,
Gunnar Braun,
Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation.
DATE 2004: 156-160 |
| 49 | EE | Tim Kogel,
Malte Doerper,
Torsten Kempf,
Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs.
SAMOS 2004: 138-148 |
| 48 | EE | Andreas Wieferink,
Malte Doerper,
Tim Kogel,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
Early ISS Integration into Network-on-Chip Designs.
SAMOS 2004: 443-452 |
| 47 | EE | Jianjiang Ceng,
Weihua Sheng,
Manuel Hohenauer,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Gunnar Braun:
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting.
SAMOS 2004: 463-473 |
| 46 | EE | Hanno Scharwächter,
David Kammler,
Andreas Wieferink,
Manuel Hohenauer,
Kingshuk Karuri,
Jianjiang Ceng,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr:
ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.
SCOPES 2004: 33-46 |
| 45 | EE | Rudolf Mathar,
Heinrich Meyr:
Stochastic modeling of the convergence behavior of concatenated codes.
VTC Fall (2) 2004: 1263-1265 |
| 44 | EE | Gunnar Braun,
Achim Nohl,
Andreas Hoffmann,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1625-1639 (2004) |
| 2003 |
|---|
| 43 | EE | Tim Kogel,
Malte Doerper,
Andreas Wieferink,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks.
CODES+ISSS 2003: 7-12 |
| 42 | EE | Achim Nohl,
Volker Greive,
Gunnar Braun,
Andreas Hoffmann,
Rainer Leupers,
Oliver Schliebusch,
Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models.
DAC 2003: 262-267 |
| 41 | EE | Gunnar Braun,
Andreas Wieferink,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels.
DATE 2003: 10966-10973 |
| 40 | EE | Oliver Wahlen,
Manuel Hohenauer,
Gunnar Braun,
Rainer Leupers,
Gerd Ascheid,
Heinrich Meyr,
Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.
SCOPES 2003: 167-181 |
| 39 | EE | Oliver Wahlen,
Manuel Hohenauer,
Rainer Leupers,
Heinrich Meyr:
Instruction Scheduler Generation for Retargetable Compilation.
IEEE Design & Test of Computers 20(1): 34-41 (2003) |
| 38 | EE | Tilman Glökler,
Andreas Hoffmann,
Heinrich Meyr:
Methodical Low-Power ASIP Design Space Exploration.
VLSI Signal Processing 33(3): 229-246 (2003) |
| 2002 |
|---|
| 37 | EE | Achim Nohl,
Gunnar Braun,
Oliver Schliebusch,
Rainer Leupers,
Heinrich Meyr,
Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation.
DAC 2002: 22-27 |
| 36 | EE | Tobias Noll,
Heinrich Meyr:
Designing SoC's.
ISLPED 2002: 283 |
| 35 | EE | Oliver Wahlen,
Tilman Glökler,
Achim Nohl,
Andreas Hoffmann,
Rainer Leupers,
Heinrich Meyr:
Application specific compiler/architecture codesign: a case study.
LCTES-SCOPES 2002: 185-193 |
| 34 | EE | Oliver Schliebusch,
Andreas Hoffmann,
Achim Nohl,
Gunnar Braun,
Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA.
VLSI Design 2002: 239-244 |
| 2001 |
|---|
| 33 | EE | Holger Keding,
Martin Coors,
Olaf Lüthje,
Heinrich Meyr:
Fast Bit-True Simulation.
DAC 2001: 708-713 |
| 32 | EE | A. Lock,
Raul Camposano,
Heinrich Meyr:
The programmable platform: does one size fit all?
DATE 2001: 226-227 |
| 31 | EE | Andreas Hoffmann,
Achim Nohl,
Stefan Pees,
Gunnar Braun,
Heinrich Meyr:
Generating production quality software development tools using a machine description language.
DATE 2001: 674-678 |
| 30 | EE | Andreas Hoffmann,
Tim Kogel,
Heinrich Meyr:
A framework for fast hardware-software co-simulation.
DATE 2001: 760-765 |
| 29 | EE | Andreas Hoffmann,
Oliver Schliebusch,
Achim Nohl,
Gunnar Braun,
Oliver Wahlen,
Heinrich Meyr:
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA.
ICCAD 2001: 625-630 |
| 28 | | Gunnar Braun,
Andreas Hoffmann,
Achim Nohl,
Heinrich Meyr:
Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description.
ISSS 2001: 57-62 |
| 27 | EE | Andreas Hoffmann,
Tim Kogel,
Achim Nohl,
Gunnar Braun,
Oliver Schliebusch,
Oliver Wahlen,
Andreas Wieferink,
Heinrich Meyr:
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1338-1354 (2001) |
| 2000 |
|---|
| 26 | EE | Jens Horstmannshoff,
Heinrich Meyr:
Efficient building block based RTL code generation from synchronous data flow graphs.
DAC 2000: 552-555 |
| 25 | EE | Stefan Pees,
Andreas Hoffmann,
Heinrich Meyr:
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language.
DATE 2000: 669-673 |
| 24 | | Michael Speth,
Alexander Jansen,
Heinrich Meyr:
Iterative Multiuser Detection for Bit Interleaved Coed Modulation.
ICC (2) 2000: 894-898 |
| 23 | EE | Stefan Pees,
Andreas Hoffmann,
Heinrich Meyr:
Retargetable compiled simulation of embedded processors using a machine description language.
ACM Trans. Design Autom. Electr. Syst. 5(4): 815-834 (2000) |
| 1999 |
|---|
| 22 | EE | Stefan Pees,
Andreas Hoffmann,
Vojin Zivojnovic,
Heinrich Meyr:
LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures.
DAC 1999: 933-938 |
| 21 | EE | Jens Horstmannshoff,
Heinrich Meyr:
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs.
ISSS 1999: 38-43 |
| 1998 |
|---|
| 20 | EE | Holger Keding,
Markus Willems,
Martin Coors,
Heinrich Meyr:
FRIDGE: A Fixed-Point Design and Simulation Environment.
DATE 1998: 429-435 |
| 1997 |
|---|
| 19 | EE | Jens Horstmannshoff,
Thorsten Grötker,
Heinrich Meyr:
Mapping multirate dataflow to complex RT level hardware models.
ASAP 1997: 283- |
| 18 | EE | Stefan Pees,
Martin Vaupel,
Vojin Zivojnovic,
Heinrich Meyr:
On core and more: a design perspective for systems-on-a-chip.
ASAP 1997: 448-457 |
| 17 | EE | Markus Willems,
Volker Bürsgens,
Holger Keding,
Thorsten Grötker,
Heinrich Meyr:
System Level Fixed-Point Design Based on an Interpolative Approach.
DAC 1997: 293-298 |
| 16 | EE | Thorsten Grötker,
R. Schoenen,
Heinrich Meyr:
PCC: a modeling technique for mixed control/data flow systems.
ED&TC 1997: 482-486 |
| 15 | EE | Vojin Zivojnovic,
Steven W. K. Tjiang,
Heinrich Meyr:
Compiled Simulation of Programmable DSP Architectures.
VLSI Signal Processing 16(1): 73-80 (1997) |
| 1996 |
|---|
| 14 | EE | Vojin Zivojnovic,
Heinrich Meyr:
Compiled HW/SW Co-Simulation.
DAC 1996: 690-695 |
| 13 | EE | Vojin Zivojnovic,
Stefan Pees,
C. Schälger,
Markus Willems,
R. Schoenen,
Heinrich Meyr:
DSP Processor/Compiler Co-Design: A Quantitative Approach.
ISSS 1996: 108- |
| 12 | | Herbert Dawid,
Heinrich Meyr:
The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations.
IEEE Trans. Computers 45(3): 307-318 (1996) |
| 11 | EE | Herbert Dawid,
Gerhard Fettweis,
Heinrich Meyr:
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation.
IEEE Trans. VLSI Syst. 4(1): 17-31 (1996) |
| 1995 |
|---|
| 10 | EE | Peter Zepter,
Thorsten Grötker,
Heinrich Meyr:
Digital Receiver Design Using VHDL Generation from Data Flow Graphs.
DAC 1995: 228-233 |
| 9 | | Claus Schotten,
Heinrich Meyr:
Test Point Insertion for an Area Efficient BIST.
ITC 1995: 515-523 |
| 1994 |
|---|
| 8 | | Martin Vaupel,
Heinrich Meyr:
High Speed FIR-Filter Architectures with Scalable Sample Rates.
ISCAS 1994: 127-130 |
| 7 | | Francky Catthoor,
Ed F. Deprettere,
Yu Hen Hu,
Jan M. Rabaey,
Heinrich Meyr,
Lothar Thiele:
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.
ISCAS 1994: 129-136 |
| 6 | EE | Olaf J. Joeressen,
Martin Vaupel,
Heinrich Meyr:
High-speed VLSI architectures for soft-output viterbi decoding.
VLSI Signal Processing 8(2): 169-181 (1994) |
| 1993 |
|---|
| 5 | | K. ten Hagen,
Heinrich Meyr:
Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project.
ICCD 1993: 462-465 |
| 4 | | Vojin Zivojnovic,
Heinrich Meyr:
Design of optimum interpolation filters for digital demodulators.
ISCAS 1993: 140-143 |
| 3 | | Sebastian Ritz,
Matthias Pankert,
Vojin Zivojnovic,
Heinrich Meyr:
High-Level Software Synthesis for the Design of Communication Systems.
IEEE Journal on Selected Areas in Communications 11(3): 348-358 (1993) |
| 1991 |
|---|
| 2 | EE | Gerhard Fettweis,
Heinrich Meyr:
Feedforward architectures for parallel Viterbi decoding.
VLSI Signal Processing 3(1-2): 105-119 (1991) |
| 1990 |
|---|
| 1 | | Gerhard Fettweis,
Heinrich Meyr:
High-Rate Viterbi Processor: A Systolic Array Solution.
IEEE Journal on Selected Areas in Communications 8(8): 1520-1534 (1990) |
