Guy G. Lemieux

2009
19	EE	Johnny Tsung Lin Ho, Guy G. Lemieux: PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260
18	EE	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52
2008
17	EE	Guy G. Lemieux, Tarek A. El-Ghazawi: Designing with extreme parallelism. FPGA 2008: 1-2
16	EE	Tarek A. El-Ghazawi, Guy G. Lemieux: Extreme parallel architectures for the masses. FPGA 2008: 127-128
15	EE	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
2007
14	EE	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
13	EE	David Yeager, Darius Chiu, Guy G. Lemieux: Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP 2007: 33-40
2006
12	EE	David Grant, Scott Chin, Guy G. Lemieux: Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL 2006: 1-4
11	EE	Marvin Tom, David Leong, Guy G. Lemieux: Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD 2006: 680-687
2005
10	EE	Marvin Tom, Guy G. Lemieux: Logic block clustering of large designs for channel-width constrained FPGAs. DAC 2005: 726-731
9		Anthony J. Yu, Guy G. Lemieux: Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL 2005: 255-262
8		Anthony J. Yu, Guy G. Lemieux: FPGA Defect Tolerance: Impact of Granularity. FPT 2005: 189-196
2002
7	EE	Guy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
6	EE	Guy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
2001
5	EE	Guy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
2000
4	EE	Guy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
3	EE	R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
1998
2	EE	A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
1997
1	EE	Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic: On two-step routing for FPGAS. ISPD 1997: 60-66

Coauthor Index

1	Tarek S. Abdelrahman	[3]
2	Stephen Dean Brown	[1] [2] [3]
3	S. Caranci	[2] [3]
4	Scott Chin	[12]
5	Darius Chiu	[13]
6	D. DeVries	[3]
7	Tarek A. El-Ghazawi	[16] [17]
8	Benjamin Gamsa	[3]
9	David Grant	[12]
10	A. Grbic	[2] [3]
11	Mark R. Greenstreet	[18]
12	R. Grindley	[2] [3]
13	M. Gusat	[2] [3]
14	Johnny Tsung Lin Ho	[19]
15	R. Ho	[3]
16	Orran Krieger	[3]
17	Julien Lamoureux	[14] [15]
18	David Leong	[11]
19	Paul Leventis	[4]
20	David M. Lewis	[4] [5] [6] [7]
21	K. Loveless	[2] [3]
22	Naraig Manjikian	[2] [3]
23	P. McHardy	[3]
24	Sinisa Srbljic	[2] [3]
25	Michael Stumm	[2] [3]
26	Paul Teehan	[18]
27	Marvin Tom	[10] [11]
28	Daniel Vranesic	[1]
29	Zvonko G. Vranesic	[2] [3]
30	Steven J. E. Wilton	[14] [15]
31	David Yeager	[13]
32	Anthony J. Yu	[8] [9]
33	Zeljko Zilic	[2] [3]

Colors in the list of coauthors