| 2008 |
|---|
| 11 | EE | Wen-Ching Lin,
Jun-Hong Chen,
Ming-Der Shieh:
A new look-up table-based multiplier/squarer design for cryptosystems over GF(2m).
ISCAS 2008: 464-467 |
| 10 | EE | Jun-Hong Chen,
Wen-Ching Lin,
Hao-Hsuan Wu,
Ming-Der Shieh:
High-speed modular multiplication design for public-key cryptosystems.
ISCAS 2008: 680-683 |
| 9 | EE | Ming-Der Shieh,
Jun-Hong Chen,
Hao-Hsuan Wu,
Wen-Ching Lin:
A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem.
IEEE Trans. VLSI Syst. 16(9): 1151-1161 (2008) |
| 2007 |
|---|
| 8 | EE | Jun-Hong Chen,
Haw-Shiuan Wu,
Ming-Der Shieh,
Wen-Ching Lin:
A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem.
ISCAS 2007: 3780-3783 |
| 2006 |
|---|
| 7 | EE | Jun-Hong Chen,
Ming-Der Shieh,
Haw-Shiuan Wu,
Wen-Ching Lin:
Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation.
APCCAS 2006: 606-609 |
| 6 | EE | Ming-Der Shieh,
Yung-Kuei Lu,
Shen-Ming Chung,
Jun-Hong Chen:
Design and implementation of efficient Reed-Solomon decoders for multi-mode applications.
ISCAS 2006 |
| 5 | EE | Jing-Shiun Lin,
Chung-Kung Lee,
Ming-Der Shieh,
Jun-Hong Chen:
High-speed CRC design for 10 Gbps applications.
ISCAS 2006 |
| 4 | EE | Ming-Der Shieh,
Jun-Hong Chen,
Chien-Ming Wu:
High-Speed Design of Montgomery Inverse Algorithm over GF(2m).
IEICE Transactions 89-A(2): 559-565 (2006) |
| 2005 |
|---|
| 3 | EE | Jun-Hong Chen,
Ming-Der Shieh,
Chien-Ming Wu:
Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography.
ISCAS (5) 2005: 5254-5257 |
| 2 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. VLSI Syst. 13(4): 439-447 (2005) |
| 2004 |
|---|
| 1 | | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen,
Hsin-Fu Lo:
VLSI architecture exploration for sliding-window Log-MAP decoders.
ISCAS (2) 2004: 513-516 |
