| 2008 |
|---|
| 20 | EE | Jorge Campos,
Hussain Al-Asaad:
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions.
IEEE Trans. VLSI Syst. 16(11): 1499-1512 (2008) |
| 2007 |
|---|
| 19 | | Hussain Al-Asaad:
Efficient Global Fault Collapsing for Combinational Library Modules.
CDES 2007: 37-43 |
| 18 | EE | Ahmed Sayed,
Hussain Al-Asaad:
A New Statistical Approach for Glitch Estimation in Combinational Circuits.
ISCAS 2007: 1641-1644 |
| 2006 |
|---|
| 17 | | Ahmed Sayed,
Hussain Al-Asaad:
Survey and Evaluation of Low-Power Flip-Flops.
CDES 2006: 77-83 |
| 16 | EE | Jorge Campos,
Hussain Al-Asaad:
Circuit Profiling Mechanisms for High-Level {ATPG}.
MTV 2006: 9-14 |
| 2005 |
|---|
| 15 | | Hussain Al-Asaad,
Ganesh Valliappan,
Lourdes Ramirez:
A Novel Functional Testing and Verification Technique for Logic Circuits.
CDES 2005: 129-135 |
| 14 | | Hector Arteaga,
Hussain Al-Asaad:
On Increasing the Observability of Modern Microprocessors.
CDES 2005: 91-96 |
| 13 | | Hussain Al-Asaad:
EGFC: An exact global fault collapsing tool for combinational circuits.
Circuits, Signals, and Systems 2005: 56-61 |
| 12 | EE | Jorge Campos,
Hussain Al-Asaad:
Search-Space Optimizations for High-Level ATPG.
MTV 2005: 84-89 |
| 2004 |
|---|
| 11 | | Ahmed Sayed,
Hussain Al-Asaad:
Survey and Evaluation of Low-Power Full-Adder Cells.
ESA/VLSI 2004: 332-338 |
| 10 | | Hector Arteaga,
Hussain Al-Asaad:
Approaches for Monitoring Vectors on Microprocessor Buses.
ESA/VLSI 2004: 393-398 |
| 2003 |
|---|
| 9 | | Hussain Al-Asaad,
Alireza Sarvi:
Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling.
VLSI 2003: 51-57 |
| 2000 |
|---|
| 8 | EE | Hussain Al-Asaad,
John P. Hayes:
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits.
VTS 2000: 221-230 |
| 7 | EE | Hussain Al-Asaad,
John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation.
J. Electronic Testing 16(6): 575-589 (2000) |
| 1998 |
|---|
| 6 | EE | David Van Campenhout,
Hussain Al-Asaad,
John P. Hayes,
Trevor N. Mudge,
Richard B. Brown:
High-level design verification of microprocessors via error modeling.
ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998) |
| 5 | EE | Hussain Al-Asaad,
Brian T. Murray,
John P. Hayes:
Online BIST for Embedded Systems.
IEEE Design & Test of Computers 15(4): 17-24 (1998) |
| 4 | EE | Hussain Al-Asaad,
John P. Hayes,
Brian T. Murray:
Scalable Test Generators for High-Speed Datapath Circuits.
J. Electronic Testing 12(1-2): 111-125 (1998) |
| 1995 |
|---|
| 3 | EE | Hussain Al-Asaad,
John P. Hayes:
Design verification via simulation and automatic test pattern generation.
ICCAD 1995: 174-180 |
| 1994 |
|---|
| 2 | | Hussain Al-Asaad,
Mankuan Michael Vai,
James Feldman:
Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths.
ICCD 1994: 75-78 |
| 1993 |
|---|
| 1 | | Hussain Al-Asaad,
Elias S. Manolakos:
A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures.
DFT 1993: 56-63 |
