2008 |
17 | EE | Xiaomeng Shi,
Kiat Seng Yeo,
Jianguo Ma,
Manh Anh Do,
Erping Li:
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs.
IEEE Trans. VLSI Syst. 16(7): 922-926 (2008) |
16 | EE | Kiat Seng Yeo,
Zhi-Hui Kong,
Nukala Nishant,
Haitao Fu,
Wei Zeng:
Integrated Circuit Design Research Ranking for Worldwide Universities.
Journal of Circuits, Systems, and Computers 17(1): 141-167 (2008) |
15 | EE | Kiat Seng Yeo,
Zhi-Hui Kong:
Spicesoft: Automated Tool for Sensitivity Analysis, Performance Analysis, and Inverse Performance Analysis of Digital Circuits.
Journal of Circuits, Systems, and Computers 17(2): 221-238 (2008) |
2007 |
14 | EE | Xiaomeng Shi,
Kiat Seng Yeo,
Jianguo Ma,
Manh Anh Do:
Distortion of pulsed signals in carbon nanotube interconnects.
Microelectronics Journal 38(3): 365-370 (2007) |
2006 |
13 | EE | Xiaopeng Yu,
Manh Anh Do,
Jianguo Ma,
Kiat Seng Yeo:
A New Phase Noise Model for TSPC based divider.
VLSI-SoC 2006: 348-351 |
12 | EE | Shan Jiang,
Manh Anh Do,
Kiat Seng Yeo:
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.
VLSI-SoC 2006: 352-356 |
11 | EE | J. J. Liu,
Manh Anh Do,
X. P. Yu,
Kiat Seng Yeo,
Shan Jiang,
Jianguo Ma:
Cmos Even Harmonic Switching mixer for Direct Conversion Receivers.
Journal of Circuits, Systems, and Computers 15(2): 183-196 (2006) |
2005 |
10 | EE | Lin Jia,
Jianguo Ma,
Kiat Seng Yeo,
Manh Anh Do:
A novel methodology for the design of LC tank VCO with low phase noise.
ISCAS (1) 2005: 376-379 |
9 | EE | Myint Wai Phyu,
Wang Ling Goh,
Kiat Seng Yeo:
A low-power static dual edge-triggered flip-flop using an output-controlled discharge configuration.
ISCAS (3) 2005: 2429-2432 |
8 | EE | Wei Meng Lim,
Han Guo Ma,
Manh Anh Do,
Kiat Seng Yeo:
A 5GHz to 6GHz integrated differential LNA.
ISCAS (5) 2005: 4815-4818 |
7 | EE | X. P. Yu,
Manh Anh Do,
Jianguo Ma,
Kiat Seng Yeo:
A new 5 GHz CMOS dual-modulus prescaler.
ISCAS (5) 2005: 5027-5030 |
6 | EE | Xiaomeng Shi,
Jianguo Ma,
Kiat Seng Yeo,
Manh Anh Do,
Erping Li:
Equivalent circuit model of on-wafer CMOS interconnects for RFICs.
IEEE Trans. VLSI Syst. 13(9): 1060-1071 (2005) |
5 | EE | X. P. Yu,
Manh Anh Do,
Lin Jia,
Jianguo Ma,
Kiat Seng Yeo:
Design of a low power wide-band high resolution programmable frequency divider.
IEEE Trans. VLSI Syst. 13(9): 1098-1103 (2005) |
4 | EE | Zhi-Hui Kong,
Kiat Seng Yeo,
Chip-Hong Chang:
An Ultra Low-power Current-mode Sense Amplifier for Sram Applications.
Journal of Circuits, Systems, and Computers 14(5): 939-952 (2005) |
2004 |
3 | EE | Beng Hwee Ong,
Choon Beng Sia,
Kiat Seng Yeo,
Jianguo Ma,
Manh Anh Do,
Erping Li:
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling.
SLIP 2004: 31-38 |
2003 |
2 | EE | Lin Jia,
Alper Cabuk,
Jianguo Ma,
Kiat Seng Yeo:
A 52 GHz VCO with Low Phase Noise Implemented in SiGe BiCMOS Technology.
IWSOC 2003: 264-269 |
2002 |
1 | EE | Jiangmin Gu,
Chip-Hong Chang,
Kiat Seng Yeo:
An interconnect optimized floorplanning of a scalar product macrocell.
ISCAS (1) 2002: 465-468 |