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Norbert Felber

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2008
24EESimon Heinzle, Olivier Saurer, Sebastian Axmann, Diego Browarnik, Andreas Schmidt, Flavio Carbognani, Peter Luethi, Norbert Felber, Markus H. Gross: A transform, lighting and setup ASIC for surface splatting. ISCAS 2008: 2813-2816
23EEPeter Luethi, Markus Wenk, Thomas Koch, Wolfgang Fichtner, Michael Lerjen, Norbert Felber: Multi-user MIMO testbed. WINTECH 2008: 109-110
22EEFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. IEEE Trans. VLSI Syst. 16(7): 830-836 (2008)
2007
21EEC. Hess, Markus Wenk, Andreas Burg, Peter Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner: Reduced-complexity mimo detector with close-to ml error rate performance. ACM Great Lakes Symposium on VLSI 2007: 200-203
20EEStefan Lemsitzer, Johannes Wolkerstorfer, Norbert Felber, Matthias Braendli: Multi-gigabit GCM-AES Architecture Optimized for FPGAs. CHES 2007: 227-238
19EESimon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner: FFT Processor for OFDM Channel Estimation. ISCAS 2007: 1417-1420
18EEPeter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner: VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. ISCAS 2007: 1421-1424
17EETim Weyrich, Simon Heinzle, Timo Aila, Daniel Bernhard Fasnacht, Stephan Oetiker, Mario Botsch, Cyril Flaig, Simon Mall, Kaspar Rohrer, Norbert Felber, Hubert Kaeslin, Markus H. Gross: A hardware architecture for surface splatting. ACM Trans. Graph. 26(3): 90 (2007)
2006
16EEFrank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159
15EEFelix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. DAC 2006: 558-561
14EEFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Two-phase resonant clocking for ultra-low-power hearing aid applications. DATE 2006: 73-78
13EEFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: 42% power savings through glitch-reducing clocking strategy in a hearing aid application. ISCAS 2006
12EEAndreas Burg, Simon Haene, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner: Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. ISCAS 2006
11EEMarkus Wenk, M. Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner: K-best MIMO detection VLSI architectures achieving up to 424 Mbps. ISCAS 2006
10EESimon Haene, Andreas Burg, David Perels, Peter Luethi, Norbert Felber, Wolfgang Fichtner: Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. ISCAS 2006
9EEFrank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electr. Notes Theor. Comput. Sci. 146(2): 133-149 (2006)
2005
8EEFlavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. PATMOS 2005: 446-455
2004
7EEFrank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin: A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44
2002
6EEThomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner: A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189
2001
5EEJ. Thalheim, Norbert Felber, Wolfgang Fichtner: A new approach for controlling series-connected IGBT modules. ISCAS (3) 2001: 69-72
4EEManfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner: Design and Verification of a Stack Processor Virtual Component. IEEE Micro 21(2): 69-80 (2001)
1999
3 Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann: Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. ITC 1999: 414-420
1993
2 H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner: VINCI: Secure Test of a VLSI High-Speed Encryption System. ITC 1993: 782-790
1991
1 H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, Xuejia Lai: VLSI Implementation of a New Block Cipher. ICCD 1991: 510-513

Coauthor Index

1Timo Aila [17]
2Sebastian Axmann [24]
3H. Bonnenberg [1] [2]
4Mario Botsch [17]
5Matthias Braendli [20]
6Diego Browarnik [24]
7Andreas Burg [7] [10] [11] [12] [18] [19] [21]
8Felix Bürgin [8] [13] [14] [15] [22]
9Flavio Carbognani [8] [13] [14] [15] [22] [24]
10Andreas Curiger [1] [2]
11Daniel Bernhard Fasnacht [17]
12Wolfgang Fichtner [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [18] [19] [21] [22] [23]
13Cyril Flaig [17]
14D. Gasser [7]
15Markus H. Gross [17] [24]
16Frank K. Gürkaynak [6] [7] [9] [16]
17Simon Haene [10] [12] [18] [19]
18Martin Hediger [15]
19Simon Heinzle [17] [24]
20C. Hess [21]
21F. Hug [7]
22Hubert Kaeslin [1] [2] [3] [4] [6] [7] [8] [9] [13] [14] [15] [16] [17] [22]
23Thomas Koch [23]
24Xuejia Lai [1]
25Stefan Lemsitzer [20]
26Michael Lerjen [23]
27Peter Luethi [10] [12] [18] [19] [21] [23] [24]
28Simon Mall [17]
29Hektor Meier [15]
30Robert Meyer-Piening [15]
31Stephan Oetiker [6] [9] [16] [17]
32David Perels [10] [12] [18]
33Kaspar Rohrer [17]
34Thomas Röwer [3] [4]
35Rafael Santschi [15]
36Olivier Saurer [24]
37Andreas Schmidt [24]
38Manfred Stadler [3] [4]
39Christoph Studer [21]
40J. Thalheim [5]
41Markus Thalmann [3] [4]
42Thomas Villiger [6]
43Markus Wenk [11] [21] [23]
44Tim Weyrich [17]
45Johannes Wolkerstorfer [20]
46M. Zellweger [11]
47R. Zimmermann [2]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)