Jui-Yuan Hsieh

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2008

2 EE Jui-Yuan Hsieh, Shanq-Jang Ruan: Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm. ASP-DAC 2008: 316-321

1 EE Shanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh: Low Power Design of Precomputation-Based Content-Addressable Memory. IEEE Trans. VLSI Syst. 16(3): 331-335 (2008)

2008
2	EE	Jui-Yuan Hsieh, Shanq-Jang Ruan: Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm. ASP-DAC 2008: 316-321
1	EE	Shanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh: Low Power Design of Precomputation-Based Content-Addressable Memory. IEEE Trans. VLSI Syst. 16(3): 331-335 (2008)

Coauthor Index

1 Shanq-Jang Ruan [1] [2]

2 Chi-Yu Wu [1]