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Kieran McLaughlin

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2008
8EEKieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll: A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. IEEE Trans. VLSI Syst. 16(7): 781-791 (2008)
2007
7EECiaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane: An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. AHS 2007: 613-618
6EEKieran McLaughlin, Sakir Sezer: High-Speed IP Address Lookups Using Hardware Based Tree Structures. AHS 2007: 625-632
5EEDwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic: An FPGA Based Memory Efficient Shared Buffer Implementation. FPL 2007: 661-664
2006
4EEFriederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny: Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW 2006: 56
3EEKieran McLaughlin, Niall O'Connor, Sakir Sezer: Exploring CAM Design For Network Processing Using FPGA Technology. AICT/ICIW 2006: 84
2EEKieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny: Design and analysis of matching circuit architectures for a closest match lookup. IPDPS 2006
2005
1EEKieran McLaughlin, Stephen O'Kane, Sakir Sezer: Implementing High Speed IP Address Lookups in Hardware. AICT/SAPIR/ELETE 2005: 140-144

Coauthor Index

1Holger Blume [2] [4] [8]
2Dwayne Burns [5] [7]
3Kevin Cackovic [5]
4Michael Hutton (Michael D. Hutton, Mike Hutton) [5]
5Friederich Kupzog [2] [4] [8]
6John V. McCanny [2] [4]
7Tobias G. Noll [2] [4] [8]
8Niall O'Connor [3]
9Stephen O'Kane [1] [7]
10Sakir Sezer [1] [2] [3] [4] [5] [6] [7] [8]
11Ciaran Toal [5] [7]
12Xin Yang [8]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)