Mateusz Majer

2008
21	EE	Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele: Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC 2008: 148-158
20	EE	Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, T. Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker: Fine grain reconfigurable architectures. FPL 2008: 348
19	EE	Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich: Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. VLSI Syst. 16(9): 1210-1219 (2008)
2007
18	EE	Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda: The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. VLSI Signal Processing 47(1): 15-31 (2007)
17	EE	Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it - Information Technology 49(3): 143- (2007)
2006
16		Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich: A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops 2006: 183-194
15	EE	Diana Göhringer, Mateusz Majer, Jürgen Teich: Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures 2006
14	EE	Mateusz Majer: An FPGA-Based Dynamically Reconfigurable Platform: From Concept to Realization. FPL 2006: 1-2
13	EE	Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich: Minimizing Communication Cost for Reconfigurable Slot Modules. FPL 2006: 1-6
2005
12		Christophe Bobda, Ali Ahmadinia, Kurapati Rajesham, Mateusz Majer, Adronis Niyonkuru: Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs. ARCS Workshops 2005: 61-66
11		Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
10	EE	Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM 2005: 319-320
9		Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL 2005: 153-158
8		Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich: The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT 2005: 37-42
7	EE	Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping 2005: 84-90
6	EE	Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich: Packet Routing in Dynamically Changing Networks on Chip. IPDPS 2005
5	EE	Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices CoRR abs/cs/0503066: (2005)
4	EE	Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen: DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices CoRR abs/cs/0510039: (2005)
2004
3	EE	Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner: Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418
2	EE	Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich: A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL 2004: 1032-1036
1	EE	Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich: Task scheduling for heterogeneous reconfigurable computers. SBCCI 2004: 22-27

Coauthor Index

1	Ali Ahmadinia	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [16] [18] [19]
2	Josef Angermeier	[17] [20] [21]
3	Ulrich Batzer	[21]
4	Jürgen Becker	[20]
5	Bernd Bleisteiner	[3]
6	Christophe Bobda	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [16] [18]
7	Lars Braun	[20]
8	Christopher Claus	[20] [21]
9	Ji Ding	[5] [7]
10	Sándor P. Fekete	[4] [5] [7] [9] [10] [11] [13] [17] [19]
11	Manfred Glesner	[3]
12	Diana Göhringer	[15] [17] [19]
13	Philipp Graf	[20]
14	Thomas Haller	[8] [10]
15	Frank Hannig	[11]
16	Ulrich Heinkel	[3]
17	Andreas Herkersdorf	[20]
18	Michael Hübner	[20]
19	Dirk Koch	[1] [2]
20	André Linarth	[8] [10]
21	Enno Lübbers	[20]
22	Renate Merker	[20]
23	Tudor Murgan	[3]
24	Adronis Niyonkuru	[12]
25	Mihail Petrov	[3]
26	Marco Platzner	[20]
27	Jörg Pleickhardt	[3]
28	Kurapati Rajesham	[12]
29	Markus Rullmann	[20]
30	T. Schwalb	[20]
31	Walter Stechele	[20] [21]
32	Jürgen Teich	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [13] [15] [16] [17] [18] [19] [20] [21]
33	Jan van der Veen	[4] [5] [7] [9] [10] [11] [13] [17] [19]
34	Peter Zipf	[3]